add support for wake and wit (#2010)
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global def hardfloatScalaModule =
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makeScalaModuleFromJSON here "hardfloat"
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| setScalaModuleRootDir "berkeley-hardfloat"
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| setScalaModuleDeps (chisel3ScalaModule, Nil)
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| setScalaModuleScalacOptions ("-Xsource:2.11", Nil)
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global def rocketchipMacros =
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makeScalaModuleFromJSON here "rocketchipMacros"
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| setScalaModuleRootDir "rocket-chip/macros"
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| addMacrosParadiseCompilerPlugin
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global def rocketchipScalaModule =
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makeScalaModuleFromJSON here "rocketchip"
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| setScalaModuleRootDir "rocket-chip"
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| setScalaModuleDeps (rocketchipMacros, hardfloatScalaModule, Nil)
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| setScalaModuleScalacOptions ("-Xsource:2.11", Nil)
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| addMacrosParadiseCompilerPlugin
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def vlsi_mem_gen = source "rocket-chip/scripts/vlsi_mem_gen"
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def vlsi_rom_gen = source "rocket-chip/scripts/vlsi_rom_gen"
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tuple VLSIRomGenOptions =
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global ConfFile: Path
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global HexFile: String
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global OutputFile: String
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global def makeVLSIRomGenOptions confFile hexFile outputFile = VLSIRomGenOptions confFile hexFile outputFile
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global def rocket_vlsi_rom_gen options =
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def cmdline =
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def confFile = options.getVLSIRomGenOptionsConfFile.getPathName
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def hexFile = options.getVLSIRomGenOptionsHexFile
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vlsi_rom_gen.getPathName, confFile, hexFile, Nil
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def inputs =
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def confFile = options.getVLSIRomGenOptionsConfFile
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def outputFile = options.getVLSIRomGenOptionsOutputFile
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def outputDir = simplify "{outputFile}/.." | mkdir
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vlsi_rom_gen, confFile, outputDir, Nil
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def outputFile = options.getVLSIRomGenOptionsOutputFile
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match (job cmdline inputs | getJobStdout)
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Pass content = write outputFile content
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Fail error = makeBadPath error
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tuple VLSIMemGenOptions =
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global BlackBox: Boolean
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global ConfFile: Path
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global OutputFile: String
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global def makeVLSIMemGenOptions confFile outputFile = VLSIMemGenOptions False confFile outputFile
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global def rocket_vlsi_mem_gen options =
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def cmdline =
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def blackBox = if options.getVLSIMemGenOptionsBlackBox then "-b", Nil else Nil
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def outputFile = "-o", options.getVLSIMemGenOptionsOutputFile, Nil
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def confFile = options.getVLSIMemGenOptionsConfFile.getPathName, Nil
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vlsi_mem_gen.getPathName, (blackBox ++ outputFile ++ confFile)
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def inputs =
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def confFile = options.getVLSIMemGenOptionsConfFile
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def outputFile = options.getVLSIMemGenOptionsOutputFile
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def outputDir = simplify "{outputFile}/.." | mkdir
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vlsi_mem_gen, confFile, outputDir, Nil
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job cmdline inputs | getJobOutput
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tuple RocketChipGeneratorOptions =
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global Jars: List Path
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global TargetDir: Path
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global TopModuleName: String
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global ConfigNames: List String
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global ExtraSources: List Path
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global def makeRocketChipGeneratorOptions jars targetDir topModule configs =
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RocketChipGeneratorOptions jars targetDir topModule configs Nil
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tuple RocketChipGeneratorOutputs =
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DTS_: Path
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FirrtlFile_: Path
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FirrtlAnnoFile_: Path
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RomConf_: Path
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AllOutputs_: List Path
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InputOptions_: RocketChipGeneratorOptions
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OMFile_: Option Path
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global def getRocketChipGeneratorOutputsDTS = getRocketChipGeneratorOutputsDTS_
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global def getRocketChipGeneratorOutputsFirrtlFile = getRocketChipGeneratorOutputsFirrtlFile_
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global def getRocketChipGeneratorOutputsFirrtlAnnoFile = getRocketChipGeneratorOutputsFirrtlAnnoFile_
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global def getRocketChipGeneratorOutputsRomConf = getRocketChipGeneratorOutputsRomConf_
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global def getRocketChipGeneratorOutputsAllOutputs = getRocketChipGeneratorOutputsAllOutputs_
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global def getRocketChipGeneratorOutputsInputOptions = getRocketChipGeneratorOutputsInputOptions_
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global def getRocketChipGeneratorOutputsObjectModelFile = getRocketChipGeneratorOutputsOMFile_
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global def runRocketChipGenerator options =
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def jars = options.getRocketChipGeneratorOptionsJars
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def runDir = "rocket-chip"
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def targetDir = options.getRocketChipGeneratorOptionsTargetDir
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def cmdline =
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def rootPackage = "_root_"
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def main = "freechips.rocketchip.system.Generator"
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def configs = catWith "_" options.getRocketChipGeneratorOptionsConfigNames
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def topModule = options.getRocketChipGeneratorOptionsTopModuleName
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def relJars = jars | map getPathName | map (relative runDir)
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def classpath = catWith ":" relJars
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def relTargetDir = relative runDir targetDir.getPathName
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which "java", "-cp", classpath, main,
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relTargetDir,
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rootPackage, topModule,
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rootPackage, configs,
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Nil
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def inputs =
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def bootrom = source 'rocket-chip/bootrom/bootrom.img'
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def extras = options.getRocketChipGeneratorOptionsExtraSources
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(bootrom, targetDir, extras) ++ jars
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def generatorJob =
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makePlan cmdline inputs
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| setPlanDirectory runDir
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| runJob
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def filterFiles regex = filter (matches regex _.getPathName) allOutputs
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def getFile regex = filterFiles regex | head | getOrElse (makeBadPath (makeError "File not found"))
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def getFileOpt regex = match (filterFiles regex)
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Nil = None
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head, tail = Some head
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def allOutputs = generatorJob.getJobOutputs
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def annoFile = getFile `.*\.anno\.json`
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def firrtlFile = getFile `.*\.fir`
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def romConfFile = getFile `.*\.rom\.conf`
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def dtsFile = getFile `.*\.dts`
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def omFile = getFileOpt `.*\.objectModel\.json`
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RocketChipGeneratorOutputs dtsFile firrtlFile annoFile romConfFile allOutputs options omFile
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@ -0,0 +1,23 @@
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{
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"hardfloat": {
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"scalaVersion": "2.12.8"
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},
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"rocketchipMacros": {
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"scalaVersion": "2.12.8",
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"dependencies": [
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"org.scala-lang:scala-reflect:2.12.8"
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]
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},
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"rocketchip": {
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"scalaVersion": "2.12.8",
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"dependencies": [
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"org.json4s::json4s-jackson:3.5.3"
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]
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},
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"macrosParadise": {
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"scalaVersion": "2.12.8",
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"dependencies": [
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"org.scalamacros:::paradise:2.1.0"
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]
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}
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}
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@ -0,0 +1,22 @@
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[
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{
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"commit": "70c1e1dd0954bb8e9d62563b8c9730bbc39d2bf0",
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"name": "berkeley-hardfloat",
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"source": "git@github.com:ucb-bar/berkeley-hardfloat.git"
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},
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{
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"commit": "258e0bd41ddc8811725d51192a8fffb133b6f1c8",
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"name": "api-chisel3-sifive",
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"source": "git@github.com:sifive/api-chisel3-sifive.git"
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},
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{
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"commit": "e1aa5f3f5c0cdeb204047c3ca50801d9f7ea25f1",
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"name": "chisel3",
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"source": "git@github.com:freechipsproject/chisel3.git"
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},
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{
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"commit": "228c9a4b7432ac52178d63b8f27fe064aec71e9c",
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"name": "firrtl",
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"source": "git@github.com:freechipsproject/firrtl.git"
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}
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]
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