diff --git a/chisel3 b/chisel3
index 07fa5622..b5a53491 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit 07fa5622ccc995f925d6d967d2a386540c9064cc
+Subproject commit b5a534914795d9d17f4dfe623525f1b804e4c60f
diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index 16f894c1..640ba6f0 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -25,6 +25,8 @@
 #include "emulator_type.h"
 
 htif_emulator_t* htif;
+bool verbose;
+
 void handle_sigterm(int sig)
 {
   htif->stop();
@@ -41,7 +43,6 @@ int main(int argc, char** argv)
   const char* loadmem = NULL;
   FILE *vcdfile = NULL;
   bool dramsim2 = false;
-  bool log = false;
   bool print_cycles = false;
   uint64_t memsz_mb = MEM_SIZE / (1024*1024);
   mm_t *mm[N_MEM_CHANNELS];
@@ -58,7 +59,7 @@ int main(int argc, char** argv)
     else if (arg == "+dramsim")
       dramsim2 = true;
     else if (arg == "+verbose")
-      log = true;
+      verbose = true;
     else if (arg.substr(0, 12) == "+max-cycles=")
       max_cycles = atoll(argv[i]+12);
     else if (arg.substr(0, 9) == "+loadmem=")
@@ -304,7 +305,7 @@ int main(int argc, char** argv)
       tile.Top__io_host_out_ready = LIT<1>(1);
     }
 
-    if (log && (trace_count >> 1) >= start)
+    if (verbose && (trace_count >> 1) >= start)
       tile.print(stderr);
 
     // make sure we dump on cycle 0 to get dump_init
@@ -356,7 +357,7 @@ int main(int argc, char** argv)
     fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count >> 1);
     ret = 2;
   }
-  else if (log || print_cycles)
+  else if (verbose || print_cycles)
   {
     fprintf(stderr, "Completed after %ld cycles\n", trace_count >> 1);
   }
diff --git a/csrc/verilator.h b/csrc/verilator.h
new file mode 100644
index 00000000..41fe2b5c
--- /dev/null
+++ b/csrc/verilator.h
@@ -0,0 +1,6 @@
+#ifndef _ROCKET_VERILATOR_H
+#define _ROCKET_VERILATOR_H
+
+extern bool verbose;
+
+#endif
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index ae1e3265..9c8f1bcf 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -56,8 +56,9 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
 
 # Run Verilator to produce a fast binary to emulate this circuit.
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
-VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=$(MODEL).reset --assert \
-	-Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT
+VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \
+	-Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT \
+  -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
 cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
 
 model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
@@ -73,12 +74,12 @@ $(emu): $(verilog) $(cppfiles) libdramsim.a $(consts_header) $(INSTALLED_VERILAT
 	mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
 	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-	-CFLAGS "$(CXXFLAGS) -DVERILATOR -I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)"
+	-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)"
 	$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
 
 $(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
 	mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG)  --trace \
 	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-	-CFLAGS "$(CXXFLAGS) -DVERILATOR -I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)"
+	-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)"
 	$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
diff --git a/firrtl b/firrtl
index cc4e7e39..860b04ef 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit cc4e7e39ebad106ff72f7ac97dcdc99048ee5347
+Subproject commit 860b04eff7758c3efae09fb0b5b908abad3b4593
diff --git a/riscv-tools b/riscv-tools
index 67484877..ba7efc42 160000
--- a/riscv-tools
+++ b/riscv-tools
@@ -1 +1 @@
-Subproject commit 6748487730cbac62122a26aa11f458b7c1495f63
+Subproject commit ba7efc42d04bcd1dacd8545acba58894aacc8c9e
diff --git a/rocket b/rocket
index 2791b6c4..94096e83 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 2791b6c446c13c0b6663177269024cfa8a4c6c26
+Subproject commit 94096e83ed58f2afaacdeb99ed2d885e3589d3f6