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Support CFLUSH.D.L1 rs1 address argument 

When rs1 = x0, it flushes the whole cache.

When rs1 != x0, it flushes the line containing the address in rs1.
This commit is contained in:
Andrew Waterman 2019-02-08 23:57:58 -08:00
parent 4c1292f96b
commit 4680989714
3 changed files with 3 additions and 3 deletions
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2
src/main/scala/rocket/IDecode.scala
View File

@ -137,7 +137,7 @@ class CFlushDecode(implicit val p: Parameters) extends DecodeConstants
{
val table: Array[(BitPat, List[BitPat])] = Array(
CFLUSH_D_L1->
List(Y,N,N,N,N,N,N,X,N,A2_X, A1_X, IMM_X, DW_X, FN_X, Y,M_FLUSH_ALL,MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N))
List(Y,N,N,N,N,N,N,Y,N,A2_X, A1_X, IMM_X, DW_X, FN_X, Y,M_FLUSH_ALL,MT_X, N,N,N,N,N,N,N,CSR.I,N,N,N,N))
}
class SDecode(implicit val p: Parameters) extends DecodeConstants

2
src/main/scala/rocket/Instructions.scala
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@ -102,7 +102,7 @@ object Instructions {
def SFENCE_VMA = BitPat("b0001001??????????000000001110011")
def WFI = BitPat("b00010000010100000000000001110011")
def CEASE = BitPat("b00110000010100000000000001110011")
def CFLUSH_D_L1 = BitPat("b11111100000000000000000001110011")
def CFLUSH_D_L1 = BitPat("b111111000000?????000000001110011")
def CSRRW = BitPat("b?????????????????001?????1110011")
def CSRRS = BitPat("b?????????????????010?????1110011")
def CSRRC = BitPat("b?????????????????011?????1110011")

2
src/main/scala/rocket/RocketCore.scala
View File

@ -399,7 +399,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
}
ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush
ex_reg_load_use := id_load_use
when (id_sfence) {
when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_FLUSH_ALL)) {
ex_ctrl.mem_type := Cat(id_raddr2 =/= UInt(0), id_raddr1 =/= UInt(0))
}