diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala
index 997d1f5e..0f41042b 100644
--- a/src/main/scala/uncore/tilelink2/Parameters.scala
+++ b/src/main/scala/uncore/tilelink2/Parameters.scala
@@ -173,10 +173,14 @@ case class TLManagerParameters(
   })
 }
 
-case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes: Int)
+case class TLManagerPortParameters(
+  managers:   Seq[TLManagerParameters],
+  beatBytes:  Int,
+  minLatency: Int = 0)
 {
   require (!managers.isEmpty)
   require (isPow2(beatBytes))
+  require (minLatency >= 0)
 
   // Require disjoint ranges for Ids and addresses
   managers.combinations(2).foreach({ case Seq(x,y) =>
@@ -291,9 +295,11 @@ case class TLClientParameters(
 
 case class TLClientPortParameters(
   clients:       Seq[TLClientParameters],
-  unsafeAtomics: Boolean = false) // Atomics are executed as get+put
+  unsafeAtomics: Boolean = false,
+  minLatency:    Int = 0) // Atomics are executed as get+put
 {
   require (!clients.isEmpty)
+  require (minLatency >= 0)
 
   // Require disjoint ranges for Ids
   clients.combinations(2).foreach({ case Seq(x,y) =>
diff --git a/src/main/scala/uncore/tilelink2/TLNodes.scala b/src/main/scala/uncore/tilelink2/TLNodes.scala
index e06e4d9a..9bbe91fe 100644
--- a/src/main/scala/uncore/tilelink2/TLNodes.scala
+++ b/src/main/scala/uncore/tilelink2/TLNodes.scala
@@ -41,8 +41,8 @@ case class TLInputNode() extends InputNode(TLImp)
 case class TLClientNode(params: TLClientParameters, numPorts: Range.Inclusive = 1 to 1)
   extends SourceNode(TLImp)(TLClientPortParameters(Seq(params)), numPorts)
 
-case class TLManagerNode(beatBytes: Int, params: TLManagerParameters, numPorts: Range.Inclusive = 1 to 1)
-  extends SinkNode(TLImp)(TLManagerPortParameters(Seq(params), beatBytes), numPorts)
+case class TLManagerNode(beatBytes: Int, params: TLManagerParameters, numPorts: Range.Inclusive = 1 to 1, minLatency: Int = 0)
+  extends SinkNode(TLImp)(TLManagerPortParameters(Seq(params), beatBytes, minLatency), numPorts)
 
 case class TLAdapterNode(
   clientFn:        Seq[TLClientPortParameters]  => TLClientPortParameters,
diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala
index afd01add..1bcbb1bb 100644
--- a/src/main/scala/uncore/tilelink2/Xbar.scala
+++ b/src/main/scala/uncore/tilelink2/Xbar.scala
@@ -47,22 +47,28 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
     clientFn  = { seq =>
       // An unsafe atomic port can not be combined with any other!
       require (!seq.exists(_.unsafeAtomics) || seq.size == 1)
-      seq(0).copy(clients = (mapInputIds(seq) zip seq) flatMap { case (range, port) =>
-        port.clients map { client => client.copy(
-          sourceId = client.sourceId.shift(range.start)
-        )}
-      })
+      seq(0).copy(
+        minLatency = seq.map(_.minLatency).min,
+        clients = (mapInputIds(seq) zip seq) flatMap { case (range, port) =>
+          port.clients map { client => client.copy(
+            sourceId = client.sourceId.shift(range.start)
+          )}
+        }
+      )
     },
     managerFn = { seq =>
       val fifoIdFactory = relabeler()
-      seq(0).copy(managers = (mapOutputIds(seq) zip seq) flatMap { case (range, port) =>
-        require (port.beatBytes == seq(0).beatBytes)
-        val fifoIdMapper = fifoIdFactory()
-        port.managers map { manager => manager.copy(
-          sinkId = manager.sinkId.shift(range.start),
-          fifoId = manager.fifoId.map(fifoIdMapper(_))
-        )}
-      })
+      seq(0).copy(
+        minLatency = seq.map(_.minLatency).min,
+        managers = (mapOutputIds(seq) zip seq) flatMap { case (range, port) =>
+          require (port.beatBytes == seq(0).beatBytes)
+          val fifoIdMapper = fifoIdFactory()
+          port.managers map { manager => manager.copy(
+            sinkId = manager.sinkId.shift(range.start),
+            fifoId = manager.fifoId.map(fifoIdMapper(_))
+          )}
+        }
+      )
     })
 
   lazy val module = new LazyModuleImp(this) {