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For per-address cache flushing, don't evict same line twice

This commit is contained in:
Andrew Waterman 2019-03-04 15:55:20 -08:00
parent 44138e3417
commit 3f962e9a3d
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/DCache.scala
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@ -332,9 +332,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
dontTouch(s2_victim_dirty)
val s2_update_meta = s2_hit_state =/= s2_new_hit_state
val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready
val s2_dont_nack_flush = supports_flush && (s2_cmd_flush_all && flushed && !flushing || s2_cmd_flush_line)
val s2_dont_nack_flush = supports_flush && (s2_cmd_flush_all && flushed && !flushing || s2_cmd_flush_line && can_acquire_before_release)
io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_flush && !s2_valid_hit
when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true }
when (io.cpu.s2_nack || s2_valid_flush_line || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true }
// tag updates on ECC errors
val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected)