replica
/
hqjenny-rocket-chip
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

fix make error mixing implicit and normal rules

This commit is contained in:
Yunsup Lee 2016-06-10 17:46:45 -07:00 committed by Palmer Dabbelt
parent 82cef6fa7b
commit 3ce8dbb6e5
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
emulator/Makefrag-verilator
View File

@ -14,12 +14,12 @@ $(FIRRTL):
.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
$(firrtl) $(params_file) $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir)"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
$(firrtl_debug) $(params_file_debug): $(chisel_srcs)
$(generated_dir_debug)/%.$(MODEL).$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)"
mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir