DTM: Don't accept DMI response when busy (#1829)
* Don't accept DMI response when DMI Busy error bit is set. * DebugTransport code cleanup
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@ -88,7 +88,6 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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val stickyBusyReg = RegInit(Bool(false))
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val stickyNonzeroRespReg = RegInit(Bool(false))
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val skipOpReg = Reg(init = Bool(false)) // Skip op because we're busy
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val downgradeOpReg = Reg(init = Bool(false)) // downgrade op because prev. failed.
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val busy = Wire(Bool())
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@ -151,11 +150,9 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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// during every CAPTURE_DR, and use the result in UPDATE_DR.
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// The sticky versions are reset by write to dmiReset in DTM_INFO.
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when (dmiAccessChain.io.update.valid) {
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skipOpReg := Bool(false)
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downgradeOpReg := Bool(false)
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}
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when (dmiAccessChain.io.capture.capture) {
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skipOpReg := busy
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downgradeOpReg := (!busy & nonzeroResp)
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stickyBusyReg := busy
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stickyNonzeroRespReg := nonzeroResp
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@ -193,16 +190,6 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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// Debug Access Chain Implementation
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dmiAccessChain.io.capture.bits := Mux(busy, busyResp, Mux(io.dmi.resp.valid, dmiResp, nopResp))
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when (dmiAccessChain.io.update.valid) {
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skipOpReg := Bool(false)
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downgradeOpReg := Bool(false)
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}
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when (dmiAccessChain.io.capture.capture) {
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skipOpReg := busy
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downgradeOpReg := (!busy & nonzeroResp)
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stickyBusyReg := busy
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stickyNonzeroRespReg := nonzeroResp
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}
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//--------------------------------------------------------
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// Drive Ready Valid Interface
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@ -211,7 +198,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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assert(!(dmiReqValidCheck && io.dmi.req.fire()), "Conflicting updates for dmiReqValidReg, should not happen.");
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when (dmiAccessChain.io.update.valid) {
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when (skipOpReg) {
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when (stickyBusyReg) {
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// Do Nothing
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}.elsewhen (downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
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//Do Nothing
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@ -234,7 +221,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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// for write operations confirm resp immediately because we don't care about data
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io.dmi.resp.valid,
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// for read operations confirm resp when we capture the data
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dmiAccessChain.io.capture.capture)
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dmiAccessChain.io.capture.capture & !busy)
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// incorrect operation - not enough time was spent in JTAG Idle state after DMI Write
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cover(dmiReqReg.op === DMIConsts.dmi_OP_WRITE & dmiAccessChain.io.capture.capture & busy, "Not enough Idle after DMI Write");
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@ -276,5 +263,4 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
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// and is used to reset the debug registers).
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io.fsmReset := tapIO.output.reset
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}
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