Optionally clock-gate the PTW
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75ee5f01df
commit
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@ -12,6 +12,7 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.util.property._
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import chisel3.internal.sourceinfo.SourceInfo
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import chisel3.experimental._
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import scala.collection.mutable.ListBuffer
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class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
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@ -70,6 +71,7 @@ class PTE(implicit p: Parameters) extends CoreBundle()(p) {
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def sx(dummy: Int = 0) = leaf() && x
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}
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@chiselName
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class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
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val io = new Bundle {
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val requestor = Vec(n, new TLBPTWIO).flip
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@ -79,9 +81,21 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(UInt(), 8)
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val state = Reg(init=s_ready)
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val arb = Module(new RRArbiter(Valid(new PTWReq), n))
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arb.io.in <> io.requestor.map(_.req)
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arb.io.out.ready := state === s_ready
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val resp_valid = Reg(next = Vec.fill(io.requestor.size)(Bool(false)))
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val clock_en = state =/= s_ready || arb.io.out.valid || io.dpath.sfence.valid || RegNext(reset)
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val gated_clock =
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if (!usingVM || !tileParams.dcache.get.clockGate) clock
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else ClockGate(clock, clock_en, "ptw_clock_gate")
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withClock (gated_clock) { // entering gated-clock domain
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val invalidated = Reg(Bool())
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val count = Reg(UInt(width = log2Up(pgLevels)))
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val resp_valid = Reg(next = Vec.fill(io.requestor.size)(Bool(false)))
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val resp_ae = RegNext(false.B)
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val resp_fragmented_superpage = RegNext(false.B)
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@ -89,10 +103,6 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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val r_req_dest = Reg(Bits())
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val r_pte = Reg(new PTE)
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val arb = Module(new RRArbiter(Valid(new PTWReq), n))
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arb.io.in <> io.requestor.map(_.req)
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arb.io.out.ready := state === s_ready
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val (pte, invalid_paddr) = {
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val tmp = new PTE().fromBits(io.mem.resp.bits.data_word_bypass)
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val res = Wire(init = new PTE().fromBits(io.mem.resp.bits.data_word_bypass))
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@ -293,7 +303,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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}
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}
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private def makePTE(ppn: UInt, default: PTE) = {
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def makePTE(ppn: UInt, default: PTE) = {
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val pte = Wire(init = default)
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pte.ppn := ppn
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pte
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@ -347,7 +357,9 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
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ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
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ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
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def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
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} // leaving gated-clock domain
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private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
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if (usingVM) cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
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}
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