Remove fsim, as it is the same as vsim, modulo CONFIG

.travis.yml

@@ -47,7 +47,6 @@ before_install:
 
 script:
   - make vsim-verilog -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
-  - make fsim-verilog -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
   - make emulator-ndebug -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
   - make emulator-regression-tests -C regression SUITE=$SUITE TORTURE_CONFIG=default CHISEL_VERSION=$CHISEL_VERSION
 

README.md

@@ -72,12 +72,7 @@ And to run the assembly tests on the C simulator and generate waveforms:
     $ make -jN run-asm-tests-debug
     $ make -jN run-bmark-tests-debug
 
-To generate FPGA-synthesizable verilog (output will be in `fsim/generated-src`):
+To generate FPGA- or VLSI-synthesizable verilog (output will be in `vsim/generated-src`):
-
-    $ cd fsim
-    $ make verilog
-
-Similarly, to generate VLSI-synthesizable verilog (output will be in `vsim/generated-src`):
 
     $ cd vsim
     $ make verilog
@@ -384,7 +379,7 @@ writeback stage. At cycle 485, there isn't a valid instruction in the
 writeback stage, perhaps, because of a instruction cache miss at PC
 0x2140.
 
-### <a name="fpga"></a> 2) Mapping a Rocket core down to an FPGA
+### <a name="fpga"></a> 2) Mapping a Rocket core to an FPGA
 
 We use Synopsys VCS for Verilog simulation. We acknowledge that using a
 proprietary Verilog simulation tool for an open-source project is not
@@ -395,14 +390,13 @@ Verilog simulator. In the meantime, you can use the C++ emulator to
 generate vcd waveforms, which you can view with an open-source waveform
 viewer such as GTKWave.
 
-So assuming you have a working Rocket chip, you can generate Verilog for
+You can generate synthesizable Verilog with the following commands:
-the FPGA tools with the following commands:
 
-    $ cd $ROCKETCHIP/fsim
+    $ cd $ROCKETCHIP/vsim
-    $ make verilog
+    $ make verilog CONFIG=DefaultFPGAConfig
 
 The Verilog used for the FPGA tools will be generated in
-fsim/generated-src. Please proceed further with the directions shown in
+vsim/generated-src. Please proceed further with the directions shown in
 the [README](https://github.com/ucb-bar/fpga-zynq/blob/master/README.md)
 of the fpga-zynq repository.
 
@@ -410,11 +404,11 @@ However, if you have access to VCS, you will be able to run assembly
 tests and benchmarks with the following commands (again assuming you
 have N cores on your host machine):
 
-    $ cd $ROCKETCHIP/fsim
+    $ cd $ROCKETCHIP/vsim
-    $ make -jN run
+    $ make -jN run CONFIG=DefaultFPGAConfig
 
 The generated output looks similar to those generated from the emulator.
-Look into fsim/output/\*.out for the output of the executed assembly
+Look into vsim/output/\*.out for the output of the executed assembly
 tests and benchmarks.
 
 ### <a name="vlsi"></a> 3) Pushing a Rocket core through the VLSI tools
@@ -485,9 +479,8 @@ Towards the end, you can also find that ExampleSmallConfig inherits all
 parameters from BaseConfig but overrides the same parameters of
 SmallConfig.
 
-Now take a look at fsim/Makefile and vsim/Makefile. Search for the
+Now take a look at vsim/Makefile. Search for the CONFIG variable.
-CONFIG variable. DefaultFPGAConfig is used for the FPGA build, while
+By default, it is set to DefaultConfig.  You can also change the
-DefaultConfig is used for the VLSI build. You can also change the
 CONFIG variable on the make command line:
 
     $ cd $ROCKETCHIP/vsim

fsim/.gitignore

@@ -1,18 +0,0 @@
-simv*
-csrc
-*.vpd
-*.key
-DVE*
-.vcs*
-timestamp
-*.out
-*.h
-*.log
-*.cmd
-*.daidir
-*.ucli
-*.a
-*.vcd
-dramsim2_ini
-generated-src
-output

fsim/Makefile

@@ -1,35 +0,0 @@
-#=======================================================================
-# Makefile for Verilog simulation w/ VCS
-#-----------------------------------------------------------------------
-# Yunsup Lee (yunsup@cs.berkeley.edu)
-#
-# This makefile will build a rtl simulator and run various tests to
-# verify proper functionality.
-#
-
-default: all
-
-base_dir = $(abspath ..)
-generated_dir = $(abspath ./generated-src)
-mem_gen = $(base_dir)/fsim/fpga_mem_gen
-sim_dir = .
-output_dir = $(sim_dir)/output
-
-BACKEND ?= v
-CONFIG ?= DefaultFPGAConfig
-TB ?= rocketTestHarness
-
-include $(base_dir)/Makefrag
-include $(sim_dir)/Makefrag
-ifneq ($(MAKECMDGOALS),clean)
--include $(generated_dir)/$(MODEL).$(CONFIG).d
-endif
-include $(base_dir)/vsim/Makefrag-verilog
-
-all: $(simv)
-debug: $(simv_debug)
-
-clean:
-	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
-
-.PHONY: default all debug clean

fsim/Makefrag

@@ -1,75 +0,0 @@
-
-#--------------------------------------------------------------------
-# Sources
-#--------------------------------------------------------------------
-
-# Verilog sources
-
-sim_vsrcs = \
-	$(generated_dir)/$(MODEL).$(CONFIG).v \
-	$(generated_dir)/consts.$(CONFIG).vh \
-	$(base_dir)/vsrc/$(TB).v \
-
-# C sources
-
-sim_csrcs = \
-	$(base_dir)/csrc/vcs_main.$(TB).cc \
-	$(base_dir)/csrc/mm.cc \
-	$(base_dir)/csrc/mm_dramsim2.cc \
-
-#--------------------------------------------------------------------
-# Build Verilog
-#--------------------------------------------------------------------
-
-verilog: $(sim_vsrcs)
-
-.PHONY: verilog
-
-#--------------------------------------------------------------------
-# Build rules
-#--------------------------------------------------------------------
-
-VCS = vcs -full64
-
-VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
-	+rad +v2k +vcs+lic+wait \
-	+vc+list -CC "-I$(VCS_HOME)/include" \
-	-CC "-I$(RISCV)/include" \
-	-CC "-I$(realpath $(base_dir))/dramsim2" \
-	-CC "-std=c++11" \
-	-CC "-Wl,-rpath,$(RISCV)/lib" \
-	-CC "-include $(consts_header)" \
-	-e vcs_main \
-	$(RISCV)/lib/libfesvr.so \
-	$(sim_dir)/libdramsim.a \
-	+incdir+$(generated_dir) \
-	+define+FPGA \
-	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
-	+define+PRINTF_COND=$(TB).verbose \
-	+libext+.v \
-
-#--------------------------------------------------------------------
-# Build the simulator
-#--------------------------------------------------------------------
-
-simv = $(sim_dir)/simv-$(MODEL)-$(CONFIG)
-$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
-	cd $(sim_dir) && \
-	rm -rf csrc && \
-	$(VCS) $(VCS_OPTS) -o $(simv) \
-	-debug_pp \
-
-simv_debug = $(sim_dir)/simv-$(MODEL)-$(CONFIG)-debug
-$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a $(consts_header)
-	cd $(sim_dir) && \
-	rm -rf csrc && \
-	$(VCS) $(VCS_OPTS) -o $(simv_debug) \
-	+define+DEBUG -debug_pp \
-
-#--------------------------------------------------------------------
-# Run
-#--------------------------------------------------------------------
-
-seed = $(shell date +%s)
-exec_simv = $(simv) -q +ntb_random_seed_automatic
-exec_simv_debug = $(simv_debug) -q +ntb_random_seed_automatic

fsim/fpga_mem_gen

@@ -1,195 +0,0 @@
-#! /usr/bin/env python
-
-# See LICENSE for license details.
-# This is based off of reference-chip/vlsi/src/vlsi_mem_gen
-
-import sys
-import math
-
-use_latches = False
-
-
-module_template = '''module %s(
-  %s
-);
-%s
-%s
-always @(posedge CLK) begin
-  %s
-end
-%s
-
-endmodule
-
-'''
-
-
-mask_assert_template = '''
-`ifndef SYNTHESIS
-integer i;
-integer j;
-always @(posedge CLK) begin%s
-end
-`endif
-'''
-
-
-assert_template = '''
-  for (i=0; i<%d; i=i+%d) begin
-    for (j=1; j<%d; j=j+1) begin
-      if (%sM[i] != %sM[i+j]) begin
-        $fwrite(32'h80000002, "ASSERTION FAILED: write mask granularity\\n");
-        $finish;
-      end
-    end
-  end'''
-
-
-def parse_line(line):
-  name = ''
-  width = 0
-  depth = 0
-  ports = ''
-  mask_gran = 1
-  tokens = line.split()
-  i = 0
-  for i in range(0,len(tokens),2):
-    s = tokens[i]
-    if s == 'name':
-      name = tokens[i+1]
-    elif s == 'width':
-      width = int(tokens[i+1])
-    elif s == 'depth':
-      depth = int(tokens[i+1])
-    elif s == 'ports':
-      ports = tokens[i+1].split(',')
-    elif s == 'mask_gran':
-      mask_gran = int(tokens[i+1])
-    else:
-      sys.exit('%s: unknown argument %s' % (sys.argv[0], a))
-  return (name, width, depth, ports, mask_gran)
-
-
-
-def gen_range(mask_index, mask_gran, max_width):
-  return '%d:%d' % (min(mask_gran*(mask_index+1),max_width)-1,
-                    min(mask_gran*(mask_index),max_width))
-
-
-
-def gen_mem(name, width, depth, ports, mask_gran):
-  addr_width = max(math.ceil(math.log(depth)/math.log(2)),1)
-  mask_width = int(math.ceil(float(width) / mask_gran))
-  port_spec = ['input CLK', 'input RST', 'input init']
-  readports = []
-  writeports = []
-  latchports = []
-  rwports = []
-  decl = []
-  combinational = []
-  sequential = []
-  maskedports = {}
-  mask_asserts = ''
-  for pid in range(len(ports)):
-    ptype = ports[pid]
-    if ptype[0:1] == 'm':
-      ptype = ptype[1:]
-      maskedports[pid] = pid
-
-    if ptype == 'read':
-      port_spec += ['input [%d:0] R%dA' % (addr_width-1, pid)]
-      port_spec += ['input R%dE' % pid]
-      port_spec += ['output [%d:0] R%dO' % (width-1, pid)]
-      readports += [pid]
-    elif ptype == 'write':
-      port_spec += ['input [%d:0] W%dA' % (addr_width-1, pid)]
-      port_spec += ['input W%dE' % pid]
-      port_spec += ['input [%d:0] W%dI' % (width-1, pid)]
-      if pid in maskedports:
-        port_spec += ['input [%d:0] W%dM' % (width-1, pid)]
-      if not use_latches or pid in maskedports:
-        writeports += [pid]
-      else:
-        latchports += [pid]
-    elif ptype == 'rw':
-      port_spec += ['input [%d:0] RW%dA' % (addr_width-1, pid)]
-      port_spec += ['input RW%dE' % pid]
-      port_spec += ['input RW%dW' % pid]
-      if pid in maskedports:
-        port_spec += ['input [%d:0] RW%dM' % (width-1, pid)]
-      port_spec += ['input [%d:0] RW%dI' % (width-1, pid)]
-      port_spec += ['output [%d:0] RW%dO' % (width-1, pid)]
-      rwports += [pid]
-    else:
-      sys.exit('%s: unknown port type %s' % (sys.argv[0], ptype))
-
-  decl += ['reg [%d:0] ram [%d:0];' % (width-1, depth-1)]
-  decl += ['`ifndef SYNTHESIS']
-  decl += ['  integer initvar;']
-  decl += ['  initial begin']
-  decl += ['    #0.002;']
-  decl += ['    for (initvar = 0; initvar < %d; initvar = initvar+1)' % depth]
-  decl += ['      ram[initvar] = {%d {$random}};' % ((width-1)/32+1)]
-  decl += ['  end']
-  decl += ['`endif']
-
-  for pid in readports:
-    decl += ['reg [%d:0] reg_R%dA;' % (addr_width-1, pid)]
-    sequential += ['if (R%dE) reg_R%dA <= R%dA;' % (pid, pid, pid)]
-    combinational += ['assign R%dO = ram[reg_R%dA];' % (pid, pid)]
-
-  for pid in rwports:
-    decl += ['reg [%d:0] reg_RW%dA;' % (addr_width-1, pid)]
-    sequential += ['if (RW%dE && !RW%dW) reg_RW%dA <= RW%dA;' % (pid, pid, pid, pid)]
-    combinational += ['assign RW%dO = ram[reg_RW%dA];' % (pid, pid)]
-
-  for pid in latchports:
-    decl += ['reg [%d:0] latch_W%dA;' % (addr_width-1, pid)]
-    decl += ['reg [%d:0] latch_W%dI;' % (width-1, pid)]
-    decl += ['reg latch_W%dE;' % (pid)]
-    combinational += ['always @(*) begin']
-    combinational += ['  if (!CLK && W%dE) latch_W%dA <= W%dA;' % (pid, pid, pid)]
-    combinational += ['  if (!CLK && W%dE) latch_W%dI <= W%dI;' % (pid, pid, pid)]
-    combinational += ['  if (!CLK) latch_W%dE <= W%dE;' % (pid, pid)]
-    combinational += ['end']
-    combinational += ['always @(*)']
-    combinational += ['  if (CLK && latch_W%dE)' % (pid)]
-    combinational += ['    ram[latch_W%dA] <= latch_W%dI;' % (pid, pid)]
-
-  for pid in writeports:
-    if pid not in maskedports:
-      sequential += ['if (W%dE) ram[W%dA] <= W%dI;' % (pid, pid, pid)]
-    else:
-      for mask_index in range(mask_width):
-        rs = gen_range(mask_index, mask_gran, width)
-        sequential += ['if (W%dE && W%dM[%d]) ram[W%dA][%s] <= W%dI[%s];' %
-                       (pid, pid, mask_index*mask_gran, pid, rs, pid, rs)]
-      mask_asserts += assert_template % (mask_width, mask_gran, mask_gran, 'W'+str(pid), 'W'+str(pid))
-  for pid in rwports:
-    if pid not in maskedports:
-      sequential += ['if (RW%dE && RW%dW) ram[RW%dA] <= RW%dI;' % (pid, pid, pid, pid)]
-    else:
-      for mask_index in range(mask_width):
-        rs = gen_range(mask_index, mask_gran, width)
-        sequential += ['if (RW%dE && RW%dW && RW%dM[%d]) ram[RW%dA][%s] <= RW%dI[%s];' %
-                       (pid, pid, pid, mask_index*mask_gran, pid, rs, pid, rs)]
-      mask_asserts += assert_template % (mask_width, mask_gran, mask_gran, 'RW'+str(pid), 'RW'+str(pid))
-  check_masks = '' if len(maskedports) == 0 else mask_assert_template % mask_asserts
-  return module_template % (name,
-                            ',\n  '.join(port_spec),
-                            check_masks,
-                            '\n  '.join(decl),
-                            '\n  '.join(sequential),
-                            '\n  '.join(combinational))
-
-
-
-def main():
-  if len(sys.argv) < 2:
-    sys.exit('Please give a .conf file as input')
-  for line in open(sys.argv[1]):
-    print(gen_mem(*parse_line(line)))
-
-
-if __name__ == '__main__':
-  main()

regression/Makefile

@@ -1,5 +1,5 @@
 # The default target, which runs all regression targets.
-regression: vsim-regression fsim-regression emulator-regression
+regression: vsim-regression emulator-regression
 
 # Regression targets for the various simulators.
 %-regression: %-asm-tests %-bmark-tests
@@ -36,7 +36,6 @@ include $(TOP)/Makefrag
 clean:
 	rm -rf stamps $(abspath $(RISCV))
 	$(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/vsim) clean
-	$(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/fsim) clean
 	$(MAKE) RISCV=$(RISCV) -C $(abspath $(TOP)/emulator) clean
 
 ifeq ($(SUITE),)
@@ -91,22 +90,6 @@ vsim-bmark-tests: $(VSIM_BMARK_TEST_STAMPS)
 vsim-regression-tests: $(VSIM_REGRESSION_TEST_STAMPS)
 vsim-torture: $(VSIM_TORTURE_STAMPS)
 
-FSIM_VERILOG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-verilog.stamp)
-FSIM_DEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-debug.stamp)
-FSIM_NDEBUG_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-ndebug.stamp)
-FSIM_ASM_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-asm-tests.stamp)
-FSIM_BMARK_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-bmark-tests.stamp)
-FSIM_REGRESSION_TEST_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-regression-tests.stamp)
-FSIM_TORTURE_STAMPS=$(foreach config,$(CONFIGS),stamps/$(config)/fsim-torture-$(TORTURE_CONFIG).stamp)
-
-fsim-verilog: $(FSIM_VERILOG_STAMPS)
-fsim-debug: $(FSIM_DEBUG_STAMPS)
-fsim-ndebug: $(FSIM_NDEBUG_STAMPS)
-fsim-asm-tests: $(FSIM_ASM_TEST_STAMPS)
-fsim-bmark-tests: $(FSIM_BMARK_TEST_STAMPS)
-fsim-regression-tests: $(FSIM_REGRESSION_TEST_STAMPS)
-fsim-torture: $(FSIM_TORTURE_STAMPS)
-
 submodule_names = chisel2 chisel3 context-dependent-environments dramsim2 firrtl groundtest hardfloat junctions rocket torture uncore $(ROCKETCHIP_ADDONS)
 
 # Checks out all the rocket-chip submodules
@@ -159,21 +142,6 @@ stamps/%/vsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/vsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug
 	date > $@
 
-stamps/%/fsim-verilog.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
-	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) verilog
-	date > $@
-
-stamps/%/fsim-ndebug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
-	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION)
-	date > $@
-
-stamps/%/fsim-debug.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
-	mkdir -p $(dir $@)
-	+flock -x $(dir $@)/chisel-lock $(MAKE) -C $(abspath $(TOP))/fsim CONFIG=$* RISCV=$(abspath $(RISCV)) CHISEL_VERSION=$(CHISEL_VERSION) debug
-	date > $@
-
 # Runs tests on one of the simulators
 stamps/%/emulator-asm-tests.stamp: stamps/other-submodules.stamp $(RISCV)/install.stamp
 	mkdir -p $(dir $@)