From 1f1b35b23b0aa7b9cb5aaeae2a1f7c5cc4a50b5e Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Thu, 29 Nov 2018 12:32:15 -0800
Subject: [PATCH] tile: tileControlAddr is now tile param named beuAddr

---
 src/main/scala/groundtest/TraceGen.scala |  1 +
 src/main/scala/tile/BaseTile.scala       |  1 +
 src/main/scala/tile/Core.scala           |  3 +--
 src/main/scala/tile/RocketTile.scala     | 15 ++++++++-------
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala
index ce99b6a0..3c4b150c 100644
--- a/src/main/scala/groundtest/TraceGen.scala
+++ b/src/main/scala/groundtest/TraceGen.scala
@@ -66,6 +66,7 @@ case class TraceGenParams(
     numGens: Int) extends GroundTestTileParams {
   def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p)
   val hartId = 0
+  val beuAddr = None
   val blockerCtrlAddr = None
   val name = None
 }
diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala
index 1ed0c92c..1f409f7c 100644
--- a/src/main/scala/tile/BaseTile.scala
+++ b/src/main/scala/tile/BaseTile.scala
@@ -28,6 +28,7 @@ trait TileParams {
   val dcache: Option[DCacheParams]
   val btb: Option[BTBParams]
   val hartId: Int
+  val beuAddr: Option[BigInt]
   val blockerCtrlAddr: Option[BigInt]
   val name: Option[String]
 }
diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
index 36fa97f3..0197ba29 100644
--- a/src/main/scala/tile/Core.scala
+++ b/src/main/scala/tile/Core.scala
@@ -38,7 +38,6 @@ trait CoreParams {
   val nL2TLBEntries: Int
   val mtvecInit: Option[BigInt]
   val mtvecWritable: Boolean
-  val tileControlAddr: Option[BigInt]
   def customCSRs(implicit p: Parameters): CustomCSRs = new CustomCSRs
 
   def instBytes: Int = instBits / 8
@@ -93,7 +92,7 @@ abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundl
   with HasCoreParameters
 
 class CoreInterrupts(implicit p: Parameters) extends TileInterrupts()(p) {
-  val buserror = coreParams.tileControlAddr.map(a => Bool())
+  val buserror = tileParams.beuAddr.map(a => Bool())
 }
 
 trait HasCoreIO extends HasTileParameters {
diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala
index c47115d7..a7cfa8f7 100644
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@@ -21,7 +21,7 @@ case class RocketTileParams(
     hcfOnUncorrectable: Boolean = false,
     name: Option[String] = Some("tile"),
     hartId: Int = 0,
-    beuControlAddr: Option[BigInt] = None,
+    beuAddr: Option[BigInt] = None,
     blockerCtrlAddr: Option[BigInt] = None,
     boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
     ) extends TileParams {
@@ -47,7 +47,7 @@ class RocketTile(
   }
   dtim_adapter.foreach(lm => connectTLSlave(lm.node, xBytes))
 
-  val bus_error_unit = tileParams.beuControlAddr map { a =>
+  val bus_error_unit = rocketParams.beuAddr map { a =>
     val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
     intOutwardNode := beu.intNode
     connectTLSlave(beu.node, xBytes)
@@ -118,18 +118,19 @@ class RocketTileModuleImp(outer: RocketTile) extends BaseTileModuleImp(outer)
     core.io.cease
   ))
 
-  outer.bus_error_unit.foreach { lm =>
-    lm.module.io.errors.dcache := outer.dcache.module.io.errors
-    lm.module.io.errors.icache := outer.frontend.module.io.errors
-  }
 
   outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
-  outer.bus_error_unit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
   halt_and_catch_fire.foreach { _ := uncorrectable }
   outer.frontend.module.io.cpu <> core.io.imem
   outer.frontend.module.io.reset_vector := constants.reset_vector
   outer.frontend.module.io.hartid := constants.hartid
 
+  outer.bus_error_unit.foreach { beu =>
+    core.io.interrupts.buserror.get := beu.module.io.interrupt
+    beu.module.io.errors.dcache := outer.dcache.module.io.errors
+    beu.module.io.errors.icache := outer.frontend.module.io.errors
+  }
+
   // Pass through various external constants and reports
   trace := core.io.trace
   core.io.hartid := constants.hartid