Howard Mao
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28faff27d3
|
run remote builds using separate ivy2/sbt directories
|
2019-09-06 18:51:55 -07:00 |
Howard Mao
|
0273cd4d90
|
add midasexamples to CI
|
2019-09-06 18:51:55 -07:00 |
Howard Mao
|
afe14d423d
|
Add FireSim tests to CI
|
2019-09-06 18:51:55 -07:00 |
abejgonzalez
|
64d2783b5f
|
use variable to control make parallelism in ci
|
2019-08-30 23:18:17 -07:00 |
abejgonzalez
|
f34a6fc523
|
reallow you to do -j for make | parallel ci runs
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2019-08-30 23:14:33 -07:00 |
Jerry Zhao
|
f221c8f26e
|
Bump boomrocket example CI build time
|
2019-08-26 20:15:01 -07:00 |
Jerry Zhao
|
ba3deac1de
|
Update CI with new config names
|
2019-08-26 14:50:46 -07:00 |
Howard Mao
|
ed85e71c79
|
fix the way header files are handled by makefiles
|
2019-08-22 07:39:33 +08:00 |
Abraham Gonzalez
|
0d218da066
|
Merge pull request #176 from ucb-bar/boom-ci
[boom] move boom integration into chipyard
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2019-08-06 22:58:36 -06:00 |
Jerry Zhao
|
a18d3ed920
|
Remove commit-on-master check
We decided this was a bad idea, and that submodules should just avoid rebase-commits.
|
2019-07-31 11:46:11 -07:00 |
abejgonzalez
|
a8dbc391a1
|
remove boom variables | update ci
|
2019-07-24 22:55:00 -07:00 |
alonamid
|
5a7ff760d1
|
Merge pull request #157 from ucb-bar/toolchains2
Toolchains build update
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2019-07-22 14:37:38 -07:00 |
alonamid
|
9e5ed591b9
|
try to fix CI
|
2019-07-22 16:54:23 +00:00 |
abejgonzalez
|
dc585609cf
|
update hwacha ci to use L2
|
2019-07-18 17:52:37 -07:00 |
Jerry Zhao
|
7a55b74ed2
|
Merge pull request #116 from ucb-bar/vlsi
Add initial VLSI flow scripts
|
2019-07-18 16:19:28 -07:00 |
abejgonzalez
|
b7bc96b6d6
|
rename missing vcs/verilator names | fix ci path
|
2019-07-16 21:36:36 -07:00 |
abejgonzalez
|
27641bdffc
|
Merge remote-tracking branch 'origin/dev' into filter-c-files
|
2019-07-16 16:56:58 -07:00 |
abejgonzalez
|
85d904f108
|
add blkdev ci | cleanup simfiles to remove duplicates
|
2019-07-16 11:34:26 -07:00 |
abejgonzalez
|
02e76f343e
|
remove commit check on firechip
|
2019-07-15 17:16:23 -07:00 |
abejgonzalez
|
c784fdc658
|
rename ci
|
2019-07-15 16:53:37 -07:00 |
Jerry Zhao
|
906f5af809
|
Don't pull hammer-cad-plugins in init script
|
2019-07-15 16:21:01 -07:00 |
abejgonzalez
|
ff945e38e5
|
run normal tests (not fast) for hwacha
|
2019-07-10 23:27:19 -07:00 |
abejgonzalez
|
cf4e383805
|
update esp tools to local dir
|
2019-07-10 21:52:00 -07:00 |
abejgonzalez
|
66443175dc
|
pass the right hash
|
2019-07-10 20:09:24 -07:00 |
abejgonzalez
|
5414df40f0
|
setup esp-tools path
|
2019-07-10 17:51:46 -07:00 |
abejgonzalez
|
9f9b7087ed
|
fix key/value store access
|
2019-07-10 15:50:22 -07:00 |
abejgonzalez
|
1abde25fd6
|
use key/value store for build strings | run simple hwacha tests
|
2019-07-10 15:39:50 -07:00 |
abejgonzalez
|
8e529e86bc
|
ensure all args are passed to run
|
2019-07-10 11:06:49 -07:00 |
abejgonzalez
|
06b45c01ed
|
use large boom configs everywhere
|
2019-07-10 09:52:44 -07:00 |
abejgonzalez
|
6469045989
|
wrap variables in runtest
|
2019-07-10 09:29:06 -07:00 |
abejgonzalez
|
fdf0edf8e0
|
fix cleanup script
|
2019-07-10 00:02:06 -07:00 |
abejgonzalez
|
82e7814205
|
add cleanup script | fix verilator unknown bin
|
2019-07-09 23:38:25 -07:00 |
abejgonzalez
|
72f4941d4b
|
update verilator_root
|
2019-07-09 18:43:22 -07:00 |
abejgonzalez
|
847a874762
|
pass correct verilator root
|
2019-07-09 18:26:37 -07:00 |
abejgonzalez
|
64daa500a0
|
pass in all args for rtl build
|
2019-07-09 17:31:04 -07:00 |
abejgonzalez
|
1094b5723e
|
bump verilator cache
|
2019-07-09 16:50:02 -07:00 |
abejgonzalez
|
f5a3ff3ac5
|
update variables | add more repos to commit check
|
2019-07-09 16:31:36 -07:00 |
abejgonzalez
|
4963b607e1
|
remove extra dependencies
|
2019-07-09 16:22:29 -07:00 |
abejgonzalez
|
3e59bc0725
|
update the readme
|
2019-07-09 16:15:04 -07:00 |
abejgonzalez
|
00d59bd25d
|
use remote build server
|
2019-07-09 16:03:25 -07:00 |
abejgonzalez
|
b556bee0b9
|
rename to "Chipyard"
|
2019-06-23 22:47:23 -07:00 |
abejgonzalez
|
bbaa8d58b0
|
switch to git branch
|
2019-06-03 09:41:56 -07:00 |
abejgonzalez
|
eb93ace725
|
check if commit is on master
|
2019-06-02 23:25:51 -07:00 |
abejgonzalez
|
c19855bfa6
|
shared heter-subsystem | single example SUB_PROJECT
|
2019-05-26 15:46:19 -07:00 |
abejgonzalez
|
6d622e7555
|
add boomrocketexample to ci
|
2019-05-23 22:00:04 -07:00 |
abejgonzalez
|
deccae4959
|
hwacha depends on esp-tools | support java args
|
2019-05-13 17:17:32 -07:00 |
abejgonzalez
|
59acd688e6
|
clearer job naming for verilog only hwacha
|
2019-05-13 14:16:11 -07:00 |
abejgonzalez
|
7ba56b58d3
|
for now just support verilog build of hwacha (no tests run on it)
|
2019-05-13 14:15:05 -07:00 |
abejgonzalez
|
a377c520a6
|
smaller rocket For hwacha ci
|
2019-05-13 13:34:29 -07:00 |
abejgonzalez
|
1226591231
|
use example config for hwacha (otherwise use other hwacha params)
|
2019-05-13 10:27:36 -07:00 |