Commit Graph

5 Commits

Author SHA1 Message Date
Howard Mao 2eeda43b93 make firrtl-interpreter a submodule instead of depending on external snapshot 2019-09-12 00:19:55 +08:00
abejgonzalez adb8897e35 add firrtl dependency to build.sbt | point to different firrtl jar | a bunch of sbt plugins 2019-04-17 23:11:14 -07:00
abejgonzalez 7d887b212c align rebar with tip of project-template master | fixes build issues 2019-04-17 16:02:44 -07:00
Paul Rigge ddf3159d61
Bump rocket, make possible to use published deps (#47)
* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
2019-03-06 18:22:21 -08:00
John Wright acd76e5410 Adding barstools to separate the top from harness and to generate the
memories as external modules, which makes VLSI flows easier to plug in.
2019-02-13 21:13:08 -08:00