65df55cf9d
add InclusiveCache
2019-07-02 16:58:08 -07:00
1f48e33be5
Bump FireSim, and add back the firrtl intrp lib dep
2019-06-28 19:16:34 +00:00
f4fb0c42b1
Fix a number of build.sbt related problems
2019-05-29 22:26:04 +00:00
a53abf1856
Bring up FireSim tests
2019-05-28 22:51:39 +00:00
2a58f387ed
Fix some test suite handling
2019-05-28 01:50:39 +00:00
c0d4e848ba
WIP
2019-05-27 22:53:05 +00:00
01067df07e
Update build.sbt with correct locations of example/utilities
2019-05-10 21:09:00 -07:00
17bc3bf60d
Decouple SUB_PROJECT builds from example
2019-05-10 02:40:16 -07:00
e0d1ba285d
Add Hwacha config to example project
2019-04-23 16:20:23 -07:00
862c217ff4
allow rocket builds | asm tests pass
2019-04-23 11:50:36 -07:00
c0b0e293c5
removed boom package and combined into example | removed example from naming | split generator file
2019-04-20 21:18:20 -07:00
e9ed53424b
add sifive blocks | add rebar configs for boom
2019-04-19 21:06:32 -07:00
eec137e1ee
make tapeout depend on testchipip for resources
2019-04-18 14:38:57 -07:00
7faaa56f34
revert condDependsOn | put new firrtl jar into rocket
2019-04-18 11:39:19 -07:00
adb8897e35
add firrtl dependency to build.sbt | point to different firrtl jar | a bunch of sbt plugins
2019-04-17 23:11:14 -07:00
68b2da6b3a
update boom | match build.sbt
2019-04-17 16:06:42 -07:00
d80acd8cf8
added boom and torture | added csmith
2019-04-15 10:17:42 -07:00
2def0dfea7
change dir structure
2019-03-12 14:30:38 -07:00
ddf3159d61
Bump rocket, make possible to use published deps ( #47 )
...
* Use published rocketchip
* Simulator works!
* Gitignore was masking csrc
* Fix broken submodules
* Update gitignore
* Fix things up
* Some more cleanup
* Clean up so that using maven works
* Incorporate feedback
* Oops
* Add workaround for some of csrc
* Forgot dtm and jtag
* Make name better and add comment
* Extraneous comment
* Fix includes.
After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.
* Add target to generate verilator-specific files.
* Ignore DS_Store
* Generate bootrom from testchipip
* Oops
* Add extraneous rocket-dsptools reference
2019-03-06 18:22:21 -08:00
acd76e5410
Adding barstools to separate the top from harness and to generate the
...
memories as external modules, which makes VLSI flows easier to plug in.
2019-02-13 21:13:08 -08:00
220aeea4c8
Bump rocket-chip
...
- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
2018-09-29 13:30:07 -07:00
a3684d01dd
use build.sbt instead of jar files to collect packages
2018-05-03 17:09:59 -07:00
28539dc562
bump rocket-chip to March commit
2018-04-16 19:33:51 -07:00
7074420aba
initial commit
2016-10-21 16:03:26 -07:00
Howard Mao