small clarifications + cleanup [skip ci]
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@ -3,7 +3,7 @@ Debugging with DTM/JTAG
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By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core.
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Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation).
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TSI simulations use the SimSerial interface to directly write the test binary into memory, while the DTM
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TSI simulations use the SimSerial interface to directly write the test binary into memory, while the DTM
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executes a small loop of code to write the test binary byte-wise into memory.
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However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system.
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@ -13,13 +13,10 @@ Creating a DTM/JTAG Config
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First, a DTM config must be created for the system that you want to create.
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This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG.
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.. code-block:: scala
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class DTMBoomConfig extends Config(
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new WithDTMTop ++
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new WithBootROM ++
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new WithJtagDTM ++
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new boom.common.SmallBoomConfig)
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.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
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:language: scala
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:start-after: DOC include start: JtagRocket
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:end-before: DOC include end: JtagRocket
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In this example, the ``WithDTMTop`` mixin specifies that the top-level SoC will instantiate a DTM.
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The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).
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@ -1,8 +1,9 @@
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Accessing Scala Resources
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===============================
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A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` functions given by FIRRTL.
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It can be used in the following way:
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A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` function given by FIRRTL.
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An example of its use can be seen in `generators/testchipip/src/main/scala/SerialAdapter.scala <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/SerialAdapter.scala>`_.
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Here is the example inlined:
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.. code-block:: scala
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@ -8,8 +8,6 @@ In order to use the parameter system correctly, we will use several terms and co
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Parameters
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--------------------
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TODO: Need to explain up, site, field, and other stuff from Henry's thesis.
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It is important to note that a significant challenge with the Rocket parameter system is being able to identify the correct parameter to use, and the impact that parameter has on the overall system.
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We are still investigating methods to facilitate parameter exploration and discovery.
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@ -7,11 +7,12 @@ SoC boots a Linux kernel and the changes you can make to customize this process.
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BootROM and RISC-V Frontend Server
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----------------------------------
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The first instructions to run when the SoC is powered on are those stored in
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the BootROM. The assembly for the BootROM code is located in
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The BootROM contains both the first instructions to run when the SoC is powered on as well as the
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Device Tree Binary (dtb) which details the components of the system.
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The assembly for the BootROM code is located in
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`generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.S <https://github.com/ucb-bar/testchipip/blob/master/src/main/resources/testchipip/bootrom/bootrom.S>`_.
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The BootROM address space starts at ``0x10000`` and execution starts at address
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``0x10040``, which is marked by the ``_hang`` label in the BootROM assembly.
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The BootROM address space starts at ``0x10000`` (determined by the ``BootROMParams`` key in the configuration) and execution starts at address
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``0x10040`` (given by the linker script and reset vector in the ``BootROMParams``), which is marked by the ``_hang`` label in the BootROM assembly.
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The Chisel generator encodes the assembled instructions into the BootROM
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hardware at elaboration time, so if you want to change the BootROM code, you
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@ -12,18 +12,10 @@ Both BOOM and Rocket have mixins labelled ``WithNBoomCores(X)`` and ``WithNBigCo
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When used together you can create a heterogeneous system.
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The following example shows a dual core BOOM with a single core Rocket.
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.. code-block:: scala
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class DualBoomAndOneRocketConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new boom.system.WithRenumberHarts ++
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new boom.common.WithRVC ++
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new boom.common.LargeBoomConfig ++
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new boom.system.WithNBoomCores(2) ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala
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:language: scala
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:start-after: DOC include start: DualBoomAndRocket
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:end-before: DOC include end: DualBoomAndRocket
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In this example, the ``WithNBoomCores`` and ``WithNBigCores`` mixins set up the default parameters for the multiple BOOM and Rocket cores, respectively.
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However, for BOOM, an extra mixin called ``LargeBoomConfig`` is added to override the default parameters with a different set of more common default parameters.
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@ -75,19 +67,10 @@ Adding Hwachas
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Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter.
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An example of adding a Hwacha to all tiles in the system is below.
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.. code-block:: scala
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class DualBoomAndRocketWithHwachasConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new hwacha.DefaultHwachaConfig ++
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new boom.system.WithRenumberHarts ++
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new boom.common.WithRVC ++
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new boom.common.LargeBoomConfig ++
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new boom.system.WithNBoomCores(2) ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala
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:language: scala
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:start-after: DOC include start: BoomAndRocketWithHwacha
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:end-before: DOC include end: BoomAndRocketWithHwacha
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In this example, Hwachas are added to both BOOM tiles and to the Rocket tile.
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All with the same Hwacha parameters.
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@ -100,24 +83,13 @@ Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on
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For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles.
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An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached.
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.. code-block:: scala
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class DualBoomAndOneHwachaRocketConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new WithMultiRoCC ++
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new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
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new boom.system.WithRenumberHarts(rocketFirst = true) ++
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new hwacha.DefaultHwachaConfig ++
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new boom.common.WithRVC ++
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new boom.common.LargeBoomConfig ++
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new boom.system.WithNBoomCores(2) ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala
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:language: scala
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:start-after: DOC include start: DualBoomAndRocketOneHwacha
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:end-before: DOC include end: DualBoomAndRocketOneHwacha
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In this example, the ``WithRenumberHarts`` relabels the ``hartId``'s of all the BOOM/Rocket cores.
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Then after that is applied to the parameters, the ``WithMultiRoCCHwacha(0)`` is used to assign to ``hartId`` zero a Hwacha (in this case ``hartId`` zero is Rocket).
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Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` is used to assign to a Hwacha accelerator to a particular ``hartId`` (in this case the ``hartId`` corresponding to Rocket).
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Finally, the ``WithMultiRoCC`` mixin is called.
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This mixin sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default.
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This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter.
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@ -105,7 +105,7 @@ the Broadcast Hub to use a bufferless design.
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The Outer Memory System
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-----------------------
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The L2 coherence agent (either L2 cache of Broadcast Hub) makes requests to
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The L2 coherence agent (either L2 cache or Broadcast Hub) makes requests to
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an outer memory system consisting of an AXI4-compatible DRAM controller.
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The default configuration uses a single memory channel, but you can configure
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@ -2,7 +2,7 @@ Berkeley Out-of-Order Machine (BOOM)
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==============================================
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The `Berkeley Out-of-Order Machine (BOOM) <https://boom-core.org/>`__ is a synthesizable and parameterizable open source RV64GC RISC-V core written in the Chisel hardware construction language.
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It serves as a drop-in replacement to the Rocket core given by Rocket Chip.
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It serves as a drop-in replacement to the Rocket core given by Rocket Chip (replaces the RocketTile with a BoomTile).
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BOOM is heavily inspired by the MIPS R10k and the Alpha 21264 out-of-order processors.
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Like the R10k and the 21264, BOOM is a unified physical register file design (also known as “explicit register renaming”).
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Conceptually, BOOM is broken up into 10 stages: Fetch, Decode, Register Rename, Dispatch, Issue, Register Read, Execute, Memory, Writeback and Commit.
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@ -28,6 +28,7 @@ class SmallBoomAndRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include start: BoomAndRocketWithHwacha
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class HwachaLargeBoomAndHwachaRocketConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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@ -38,6 +39,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: BoomAndRocketWithHwacha
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class RoccLargeBoomAndRoccRocketConfig extends Config(
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new WithTop ++
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@ -60,6 +62,7 @@ class DualLargeBoomAndRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include start: DualBoomAndRocketOneHwacha
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class DualLargeBoomAndHwachaRocketConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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@ -71,6 +74,7 @@ class DualLargeBoomAndHwachaRocketConfig extends Config(
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new boom.common.WithNBoomCores(2) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: DualBoomAndRocketOneHwacha
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class LargeBoomAndRV32RocketConfig extends Config(
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new WithTop ++
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@ -83,6 +87,7 @@ class LargeBoomAndRV32RocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include start: DualBoomAndRocket
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class DualLargeBoomAndDualRocketConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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@ -92,3 +97,4 @@ class DualLargeBoomAndDualRocketConfig extends Config(
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new boom.common.WithNBoomCores(2) ++ // 2 boom cores
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new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: DualBoomAndRocket
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@ -31,6 +31,7 @@ class RoccRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include start: JtagRocket
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class jtagRocketConfig extends Config(
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new WithDTMTop ++ // use top with dtm
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new freechips.rocketchip.subsystem.WithJtagDTM ++ // add jtag/DTM module to coreplex
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@ -38,6 +39,7 @@ class jtagRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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// DOC include end: JtagRocket
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// DOC include start: PWMRocketConfig
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class PWMRocketConfig extends Config(
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