Cleanup configs
This commit is contained in:
Jerry Zhao
parent
b09794f548
commit
e7c727372f
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@ -1 +1 @@
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Subproject commit 4e9d496d3678cc5ae005669a448ae9e89f8ae847
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Subproject commit 793912eef8a9f09c13bd791c33ba682350a6026a
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@ -3,88 +3,65 @@ package example
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import chisel3._
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import freechips.rocketchip.config.{Config}
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import freechips.rocketchip.subsystem.{WithJtagDTM}
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import boom.common._
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// ---------------------
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// BOOM Configs
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// ---------------------
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class SmallBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithBootROM ++
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new boom.common.SmallBoomConfig)
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new WithTop ++ // use normal top
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new WithBootROM ++ // use testchipip bootrom
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new boom.common.WithSmallBooms ++ // 1-wide BOOM
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new boom.common.WithNBoomCores(1) ++ // single-core
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new freechips.rocketchip.system.BaseConfig) // "Base" rocketchip system
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class MediumBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithTop ++
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new WithBootROM ++
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new boom.common.MediumBoomConfig)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithMediumBooms ++ // 2-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class LargeBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithTop ++
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new WithBootROM ++
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new boom.common.LargeBoomConfig)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithLargeBooms ++ // 3-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class MegaBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithTop ++
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new WithBootROM ++
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new boom.common.MegaBoomConfig)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithMegaBooms ++ // 4-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class jtagSmallBoomConfig extends Config(
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new WithDTMBoomRocketTop ++
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class DualSmallBoomConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new WithJtagDTM ++
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new boom.common.SmallBoomConfig)
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class jtagMediumBoomConfig extends Config(
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new WithDTMBoomRocketTop ++
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new WithBootROM ++
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new WithJtagDTM ++
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new boom.common.MediumBoomConfig)
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class jtagLargeBoomConfig extends Config(
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new WithDTMBoomRocketTop ++
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new WithBootROM ++
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new WithJtagDTM ++
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new boom.common.LargeBoomConfig)
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class jtagMegaBoomConfig extends Config(
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new WithDTMBoomRocketTop ++
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new WithBootROM ++
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new WithJtagDTM ++
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new boom.common.MegaBoomConfig)
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class SmallDualBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithBootROM ++
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new boom.common.SmallDualBoomConfig)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithSmallBooms ++
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new boom.common.WithNBoomCores(2) ++ // dual-core
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new freechips.rocketchip.system.BaseConfig)
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class TracedSmallBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithTop ++
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new WithBootROM ++
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new boom.common.TracedSmallBoomConfig)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithTrace ++ // enable trace port on BOOM
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new boom.common.WithSmallBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class SmallRV32UnifiedBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithTop ++
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new WithBootROM ++
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new boom.common.SmallRV32UnifiedBoomConfig)
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// --------------------------
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// BOOM + Rocket Configs
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// --------------------------
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class SmallBoomAndRocketConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithBootROM ++
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new boom.common.SmallBoomAndRocketConfig)
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class MediumBoomAndRocketConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithBootROM ++
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new boom.common.MediumBoomAndRocketConfig)
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class DualMediumBoomAndDualRocketConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithBootROM ++
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new boom.common.DualMediumBoomAndDualRocketConfig)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithUnifiedMemIntIQs ++ // use unified mem+int issue queues
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new boom.common.WithSmallBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, ValName}
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import freechips.rocketchip.devices.tilelink.BootROMParams
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import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC}
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import boom.system.{BoomTilesKey}
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import boom.common.{BoomTilesKey}
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import testchipip._
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@ -52,43 +52,43 @@ class WithGPIO extends Config((site, here, up) => {
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/**
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* Class to specify a "plain" top level BOOM and/or Rocket system
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*/
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class WithNormalBoomRocketTop extends Config((site, here, up) => {
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case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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Module(LazyModule(new BoomRocketTop()(p)).module)
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class WithTop extends Config((site, here, up) => {
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case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
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Module(LazyModule(new Top()(p)).module)
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}
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})
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/**
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* Class to specify a top level BOOM and/or Rocket system with DTM
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*/
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class WithDTMBoomRocketTop extends Config((site, here, up) => {
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case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
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Module(LazyModule(new BoomRocketTopWithDTM()(p)).module)
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class WithDTMTop extends Config((site, here, up) => {
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case BuildTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
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Module(LazyModule(new TopWithDTM()(p)).module)
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}
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})
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/**
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* Class to specify a top level BOOM and/or Rocket system with PWM
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*/
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class WithPWMBoomRocketTop extends Config((site, here, up) => {
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case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module)
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class WithPWMTop extends Config((site, here, up) => {
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case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new TopWithPWMTL()(p)).module)
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})
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/**
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* Class to specify a top level BOOM and/or Rocket system with a PWM AXI4
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*/
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class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => {
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case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module)
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class WithPWMAXI4Top extends Config((site, here, up) => {
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case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new TopWithPWMAXI4()(p)).module)
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})
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/**
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* Class to specify a top level BOOM and/or Rocket system with a block device
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*/
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class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
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case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
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class WithBlockDeviceModelTop extends Config((site, here, up) => {
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case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new TopWithBlockDevice()(p)).module)
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top.connectBlockDeviceModel()
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top
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}
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@ -97,9 +97,9 @@ class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
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/**
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* Class to specify a top level BOOM and/or Rocket system with a simulator block device
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*/
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class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
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case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
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class WithSimBlockDeviceTop extends Config((site, here, up) => {
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case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new TopWithBlockDevice()(p)).module)
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top.connectSimBlockDevice(clock, reset)
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top
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}
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@ -108,9 +108,9 @@ class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
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/**
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* Class to specify a top level BOOM and/or Rocket system with GPIO
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*/
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class WithGPIOBoomRocketTop extends Config((site, here, up) => {
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case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module)
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class WithGPIOTop extends Config((site, here, up) => {
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case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new TopWithGPIO()(p)).module)
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for (gpio <- top.gpio) {
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for (pin <- gpio.pins) {
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pin.i.ival := false.B
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@ -3,264 +3,100 @@ package example
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import chisel3._
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import freechips.rocketchip.config.{Config}
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import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks, WithInclusiveCache}
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import testchipip._
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// --------------
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// Rocket Configs
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// --------------
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class BaseRocketConfig extends Config(
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class RocketConfig extends Config(
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new WithTop ++ // use default top
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new WithBootROM ++ // use default bootrom
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system (implicitly creates Rocket cores)
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class HwachaRocketConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new freechips.rocketchip.system.DefaultConfig)
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class DefaultRocketConfig extends Config(
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new WithNormalBoomRocketTop ++
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new BaseRocketConfig)
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class HwachaConfig extends Config(
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new hwacha.DefaultHwachaConfig ++
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new DefaultRocketConfig)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class RoccRocketConfig extends Config(
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new WithRoccExample ++
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new DefaultRocketConfig)
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new WithTop ++
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class jtagRocketConfig extends Config(
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new WithDTMTop ++ // use top with dtm
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new freechips.rocketchip.subsystem.WithJtagDTM ++ // add jtag/DTM module to coreplex
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class PWMRocketConfig extends Config(
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new WithPWMBoomRocketTop ++
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new BaseRocketConfig)
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new WithPWMTop ++ // use top with tilelink-controlled PWM
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class PWMAXI4RocketConfig extends Config(
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new WithPWMAXI4BoomRocketTop ++
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new BaseRocketConfig)
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class PWMRAXI4ocketConfig extends Config(
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new WithPWMAXI4Top ++ // use top with axi4-controlled PWM
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class SimBlockDeviceRocketConfig extends Config(
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new WithBlockDevice ++
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new WithSimBlockDeviceBoomRocketTop ++
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new BaseRocketConfig)
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new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
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new WithSimBlockDeviceTop ++ // use top with block-device IOs and connect to simblockdevice
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class BlockDeviceModelRocketConfig extends Config(
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new WithBlockDevice ++
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new WithBlockDeviceModelBoomRocketTop ++
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new BaseRocketConfig)
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new testchipip.WithBlockDevice ++ // add block-device module to periphery bus
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new WithBlockDeviceModelTop ++ // use top with block-device IOs and connect to a blockdevicemodel
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class GPIORocketConfig extends Config(
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new WithGPIO ++
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new WithGPIOBoomRocketTop ++
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new BaseRocketConfig)
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new WithGPIO ++ // add GPIOs to the peripherybus
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new WithGPIOTop ++ // use top with GPIOs
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class DualCoreRocketConfig extends Config(
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new WithNBigCores(2) ++
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new DefaultRocketConfig)
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new WithTop ++
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // dual-core (2 RocketTiles)
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new freechips.rocketchip.system.BaseConfig)
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class RV32RocketConfig extends Config(
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new WithRV32 ++
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new DefaultRocketConfig)
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class GB1MemoryConfig extends Config(
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new WithExtMemSize((1<<30) * 1L) ++
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new DefaultRocketConfig)
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class RocketL2Config extends Config(
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new WithInclusiveCache ++
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new DefaultRocketConfig)
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class HwachaL2Config extends Config(
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new hwacha.DefaultHwachaConfig ++
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new WithInclusiveCache ++
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new DefaultRocketConfig)
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// ------------
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// BOOM Configs
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// ------------
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class BaseBoomConfig extends Config(
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new WithTop ++
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new WithBootROM ++
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new boom.common.LargeBoomConfig)
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class SmallBaseBoomConfig extends Config(
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new WithBootROM ++
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new boom.common.SmallBoomConfig)
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class DefaultBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new BaseBoomConfig)
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class SmallDefaultBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new SmallBaseBoomConfig)
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class HwachaBoomConfig extends Config(
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new hwacha.DefaultHwachaConfig ++
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new DefaultBoomConfig)
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class RoccBoomConfig extends Config(
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new WithRoccExample ++
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new DefaultBoomConfig)
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class PWMBoomConfig extends Config(
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new WithPWMBoomRocketTop ++
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new BaseBoomConfig)
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class PWMAXI4BoomConfig extends Config(
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new WithPWMAXI4BoomRocketTop ++
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new BaseBoomConfig)
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class SimBlockDeviceBoomConfig extends Config(
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new WithBlockDevice ++
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new WithSimBlockDeviceBoomRocketTop ++
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new BaseBoomConfig)
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class BlockDeviceModelBoomConfig extends Config(
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new WithBlockDevice ++
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new WithBlockDeviceModelBoomRocketTop ++
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new BaseBoomConfig)
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class GPIOBoomConfig extends Config(
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new WithGPIO ++
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new WithGPIOBoomRocketTop ++
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new BaseBoomConfig)
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/**
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* Slightly different looking configs since we need to override
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* the `WithNBoomCores` with the DefaultBoomConfig params
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*/
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class DualCoreBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithBootROM ++
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new boom.common.WithRVC ++
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new boom.common.WithLargeBooms ++
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new boom.common.BaseBoomConfig ++
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new boom.common.WithNBoomCores(2) ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.system.BaseConfig)
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class DualCoreSmallBoomConfig extends Config(
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new WithNormalBoomRocketTop ++
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new WithBootROM ++
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new boom.common.WithRVC ++
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new boom.common.WithSmallBooms ++
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new boom.common.BaseBoomConfig ++
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new boom.common.WithNBoomCores(2) ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.system.BaseConfig)
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|
||||
class RV32UnifiedBoomConfig extends Config(
|
||||
new WithNormalBoomRocketTop ++
|
||||
new WithBootROM ++
|
||||
new boom.common.SmallRV32UnifiedBoomConfig)
|
||||
|
||||
class BoomL2Config extends Config(
|
||||
new WithInclusiveCache ++
|
||||
new SmallDefaultBoomConfig)
|
||||
|
||||
// ---------------------
|
||||
// BOOM and Rocket Configs
|
||||
// ---------------------
|
||||
|
||||
class BaseBoomAndRocketConfig extends Config(
|
||||
new WithBootROM ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithRVC ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.BaseBoomConfig ++
|
||||
new boom.common.WithNBoomCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class SmallBaseBoomAndRocketConfig extends Config(
|
||||
class GB1MemoryRocketConfig extends Config(
|
||||
new WithTop ++
|
||||
new WithBootROM ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithRVC ++
|
||||
new boom.common.WithSmallBooms ++
|
||||
new boom.common.BaseBoomConfig ++
|
||||
new boom.common.WithNBoomCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 2GB simulated external memory
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class DefaultBoomAndRocketConfig extends Config(
|
||||
new WithNormalBoomRocketTop ++
|
||||
new BaseBoomAndRocketConfig)
|
||||
|
||||
class SmallDefaultBoomAndRocketConfig extends Config(
|
||||
new WithNormalBoomRocketTop ++
|
||||
new SmallBaseBoomAndRocketConfig)
|
||||
|
||||
class HwachaBoomAndRocketConfig extends Config(
|
||||
new hwacha.DefaultHwachaConfig ++
|
||||
new DefaultBoomAndRocketConfig)
|
||||
|
||||
class RoccBoomAndRocketConfig extends Config(
|
||||
new WithRoccExample ++
|
||||
new DefaultBoomAndRocketConfig)
|
||||
|
||||
class PWMBoomAndRocketConfig extends Config(
|
||||
new WithPWMBoomRocketTop ++
|
||||
new BaseBoomAndRocketConfig)
|
||||
|
||||
class PWMAXI4BoomAndRocketConfig extends Config(
|
||||
new WithPWMAXI4BoomRocketTop ++
|
||||
new BaseBoomAndRocketConfig)
|
||||
|
||||
class SimBlockDeviceBoomAndRocketConfig extends Config(
|
||||
new WithBlockDevice ++
|
||||
new WithSimBlockDeviceBoomRocketTop ++
|
||||
new BaseBoomAndRocketConfig)
|
||||
|
||||
class BlockDeviceModelBoomAndRocketConfig extends Config(
|
||||
new WithBlockDevice ++
|
||||
new WithBlockDeviceModelBoomRocketTop ++
|
||||
new BaseBoomAndRocketConfig)
|
||||
|
||||
class GPIOBoomAndRocketConfig extends Config(
|
||||
new WithGPIO ++
|
||||
new WithGPIOBoomRocketTop ++
|
||||
new BaseBoomAndRocketConfig)
|
||||
|
||||
class DualCoreBoomAndOneRocketConfig extends Config(
|
||||
new WithNormalBoomRocketTop ++
|
||||
new WithBootROM ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithRVC ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.BaseBoomConfig ++
|
||||
new boom.common.WithNBoomCores(2) ++
|
||||
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class DualBoomAndOneHwachaRocketConfig extends Config(
|
||||
new WithNormalBoomRocketTop ++
|
||||
new WithBootROM ++
|
||||
new WithMultiRoCC ++
|
||||
new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
|
||||
new boom.common.WithRenumberHarts(rocketFirst = true) ++
|
||||
new hwacha.DefaultHwachaConfig ++
|
||||
new boom.common.WithRVC ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.BaseBoomConfig ++
|
||||
new boom.common.WithNBoomCores(2) ++
|
||||
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class RV32BoomAndRocketConfig extends Config(
|
||||
new WithNormalBoomRocketTop ++
|
||||
new WithBootROM ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithBoomRV32 ++
|
||||
new boom.common.WithRVC ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.BaseBoomConfig ++
|
||||
new boom.common.WithNBoomCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
|
||||
new freechips.rocketchip.subsystem.WithRV32 ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class DualCoreRocketL2Config extends Config(
|
||||
new WithInclusiveCache ++
|
||||
new DualCoreRocketConfig)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,84 @@
|
|||
package example
|
||||
|
||||
import chisel3._
|
||||
|
||||
import freechips.rocketchip.config.{Config}
|
||||
|
||||
// ---------------------
|
||||
// Heterogenous Configs
|
||||
// ---------------------
|
||||
|
||||
class LargeBoomAndRocketConfig extends Config(
|
||||
new WithTop ++ // default top
|
||||
new WithBootROM ++ // default bootrom
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive l2
|
||||
new boom.common.WithRenumberHarts ++ // avoid hartid overlap
|
||||
new boom.common.WithLargeBooms ++ // 3-wide boom
|
||||
new boom.common.WithNBoomCores(1) ++ // single-core boom
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket
|
||||
new freechips.rocketchip.system.BaseConfig) // "Base" rocketchip system
|
||||
|
||||
class HwachaLargeBoomAndHwachaRocketConfig extends Config(
|
||||
new WithTop ++
|
||||
new WithBootROM ++
|
||||
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.WithNBoomCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class RoccLargeBoomAndRoccRocketConfig extends Config(
|
||||
new WithTop ++
|
||||
new WithBootROM ++
|
||||
new freechips.rocketchip.subsystem.WithRoccExample ++ // add example rocc accelerator to all harts
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.WithNBoomCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class DualLargeBoomAndRocketConfig extends Config(
|
||||
new WithTop ++
|
||||
new WithBootROM ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.WithNBoomCores(2) ++ // 2-boom cores
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class DualLargeBoomAndHwachaRocketConfig extends Config(
|
||||
new WithTop ++
|
||||
new WithBootROM ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new WithMultiRoCC ++ // support heterogeneous rocc
|
||||
new WithMultiRoCCHwacha(2) ++ // put hwacha on hart-2 (rocket)
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.WithNBoomCores(2) ++
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class LargeBoomAndRV32RocketConfig extends Config(
|
||||
new WithTop ++
|
||||
new WithBootROM ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.WithNBoomCores(1) ++
|
||||
new freechips.rocketchip.subsystem.WithRV32 ++ // use 32-bit rocket
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
||||
class DualLargeBoomAndDualRocketConfig extends Config(
|
||||
new WithTop ++
|
||||
new WithBootROM ++
|
||||
new freechips.rocketchip.subsystem.WithInclusiveCache ++
|
||||
new boom.common.WithRenumberHarts ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.WithNBoomCores(2) ++ // 2 boom cores
|
||||
new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
|
||||
new freechips.rocketchip.system.BaseConfig)
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
//******************************************************************************
|
||||
// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
|
||||
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
package example
|
||||
|
||||
import chisel3._
|
||||
import chisel3.internal.sourceinfo.{SourceInfo}
|
||||
|
||||
import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
|
||||
import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
|
||||
import freechips.rocketchip.tile._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.interrupts._
|
||||
import freechips.rocketchip.util._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.amba.axi4._
|
||||
|
||||
import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey}
|
||||
|
||||
|
||||
trait HasBoomAndRocketTiles extends HasTiles
|
||||
with CanHavePeripheryPLIC
|
||||
with CanHavePeripheryCLINT
|
||||
with HasPeripheryDebug
|
||||
{ this: BaseSubsystem =>
|
||||
|
||||
val module: HasBoomAndRocketTilesModuleImp
|
||||
|
||||
protected val rocketTileParams = p(RocketTilesKey)
|
||||
protected val boomTileParams = p(BoomTilesKey)
|
||||
// crossing can either be per tile or global (aka only 1 crossing specified)
|
||||
private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
|
||||
private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
|
||||
|
||||
// Make a tile and wire its nodes into the system,
|
||||
// according to the specified type of clock crossing.
|
||||
// Note that we also inject new nodes into the tile itself,
|
||||
// also based on the crossing type.
|
||||
val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) =>
|
||||
val rocket = LazyModule(new RocketTile(tp, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
|
||||
|
||||
connectMasterPortsToSBus(rocket, crossing)
|
||||
connectSlavePortsToCBus(rocket, crossing)
|
||||
|
||||
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocket.rocketLogicalTree.getOMInterruptTargets)
|
||||
LogicalModuleTree.add(logicalTreeNode, rocket.rocketLogicalTree)
|
||||
|
||||
rocket
|
||||
}
|
||||
|
||||
val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) =>
|
||||
val boom = LazyModule(new BoomTile(tp, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
|
||||
|
||||
connectMasterPortsToSBus(boom, crossing)
|
||||
connectSlavePortsToCBus(boom, crossing)
|
||||
|
||||
def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(boom.rocketLogicalTree.getOMInterruptTargets)
|
||||
LogicalModuleTree.add(logicalTreeNode, boom.rocketLogicalTree)
|
||||
|
||||
boom
|
||||
}
|
||||
|
||||
// combine tiles and connect interrupts based on the order of harts
|
||||
val boomAndRocketTiles = (rocketTiles ++ boomTiles).sortWith(_.tileParams.hartId < _.tileParams.hartId).map {
|
||||
tile => {
|
||||
connectInterrupts(tile, Some(debug), clintOpt, plicOpt)
|
||||
|
||||
tile
|
||||
}
|
||||
}
|
||||
|
||||
def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++
|
||||
(boomTiles map { t => t.module.core.coreMonitorBundle}).toList
|
||||
}
|
||||
|
||||
trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
|
||||
with HasPeripheryDebugModuleImp
|
||||
{
|
||||
val outer: HasBoomAndRocketTiles
|
||||
}
|
||||
|
||||
class Subsystem(implicit p: Parameters) extends BaseSubsystem
|
||||
with HasBoomAndRocketTiles
|
||||
{
|
||||
val tiles = boomAndRocketTiles
|
||||
override lazy val module = new SubsystemModuleImp(this)
|
||||
|
||||
def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil
|
||||
}
|
||||
|
||||
class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
|
||||
with HasResetVectorWire
|
||||
with HasBoomAndRocketTilesModuleImp
|
||||
{
|
||||
tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
|
||||
wire.hartid := i.U
|
||||
wire.reset_vector := global_reset_vector
|
||||
}
|
||||
|
||||
// create file with boom params
|
||||
ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
|
||||
}
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
//******************************************************************************
|
||||
// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
|
||||
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
package example
|
||||
|
||||
import chisel3._
|
||||
|
||||
import freechips.rocketchip.config.{Parameters}
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.util.{DontTouch}
|
||||
|
||||
// ---------------------------------------------------------------------
|
||||
// Base system that uses the debug test module (dtm) to bringup the core
|
||||
// ---------------------------------------------------------------------
|
||||
|
||||
/**
|
||||
* Base top with periphery devices and ports, and a BOOM + Rocket subsystem
|
||||
*/
|
||||
class System(implicit p: Parameters) extends Subsystem
|
||||
with HasAsyncExtInterrupts
|
||||
with CanHaveMasterAXI4MemPort
|
||||
with CanHaveMasterAXI4MMIOPort
|
||||
with CanHaveSlaveAXI4Port
|
||||
with HasPeripheryBootROM
|
||||
{
|
||||
override lazy val module = new SystemModule(this)
|
||||
|
||||
// The sbus masters the cbus; here we convert TL-UH -> TL-UL
|
||||
sbus.crossToBus(cbus, NoCrossing)
|
||||
|
||||
// The cbus masters the pbus; which might be clocked slower
|
||||
cbus.crossToBus(pbus, SynchronousCrossing())
|
||||
|
||||
// The fbus masters the sbus; both are TL-UH or TL-C
|
||||
FlipRendering { implicit p =>
|
||||
sbus.crossFromBus(fbus, SynchronousCrossing())
|
||||
}
|
||||
|
||||
// The sbus masters the mbus; here we convert TL-C -> TL-UH
|
||||
private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
|
||||
private val (in, out, halt) = coherenceManager(this)
|
||||
if (nBanks != 0) {
|
||||
sbus.coupleTo("coherence_manager") { in :*= _ }
|
||||
mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
|
||||
*/
|
||||
class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
|
||||
with HasRTCModuleImp
|
||||
with HasExtInterruptsModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
with CanHaveMasterAXI4MMIOPortModuleImp
|
||||
with CanHaveSlaveAXI4PortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
with DontTouch
|
||||
|
|
@ -14,8 +14,8 @@ import freechips.rocketchip.devices.debug.{Debug}
|
|||
// BOOM and/or Rocket Test Harness
|
||||
// -------------------------------
|
||||
|
||||
case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]]
|
||||
case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]]
|
||||
case object BuildTop extends Field[(Clock, Bool, Parameters) => TopModule[Top]]
|
||||
case object BuildTopWithDTM extends Field[(Clock, Bool, Parameters) => TopWithDTMModule[TopWithDTM]]
|
||||
|
||||
/**
|
||||
* Test harness using TSI to bringup the system
|
||||
|
|
@ -28,7 +28,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
|
|||
// force Chisel to rename module
|
||||
override def desiredName = "TestHarness"
|
||||
|
||||
val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p)
|
||||
val dut = p(BuildTop)(clock, reset.toBool, p)
|
||||
|
||||
dut.debug := DontCare
|
||||
dut.connectSimAXIMem()
|
||||
|
|
@ -63,7 +63,7 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
|
|||
// force Chisel to rename module
|
||||
override def desiredName = "TestHarness"
|
||||
|
||||
val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p)
|
||||
val dut = p(BuildTopWithDTM)(clock, reset.toBool, p)
|
||||
|
||||
dut.reset := reset.asBool | dut.debug.ndreset
|
||||
dut.connectSimAXIMem()
|
||||
|
|
|
|||
|
|
@ -16,63 +16,63 @@ import sifive.blocks.devices.gpio._
|
|||
// BOOM and/or Rocket Top Level Systems
|
||||
// ------------------------------------
|
||||
|
||||
class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem
|
||||
class Top(implicit p: Parameters) extends System
|
||||
with HasNoDebug
|
||||
with HasPeripherySerial {
|
||||
override lazy val module = new BoomRocketTopModule(this)
|
||||
override lazy val module = new TopModule(this)
|
||||
}
|
||||
|
||||
class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.BoomRocketSystemModule(l)
|
||||
class TopModule[+L <: Top](l: L) extends SystemModule(l)
|
||||
with HasNoDebugModuleImp
|
||||
with HasPeripherySerialModuleImp
|
||||
with DontTouch
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop
|
||||
class TopWithPWMTL(implicit p: Parameters) extends Top
|
||||
with HasPeripheryPWMTL {
|
||||
override lazy val module = new BoomRocketTopWithPWMTLModule(this)
|
||||
override lazy val module = new TopWithPWMTLModule(this)
|
||||
}
|
||||
|
||||
class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l)
|
||||
class TopWithPWMTLModule(l: TopWithPWMTL) extends TopModule(l)
|
||||
with HasPeripheryPWMTLModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop
|
||||
class TopWithPWMAXI4(implicit p: Parameters) extends Top
|
||||
with HasPeripheryPWMAXI4 {
|
||||
override lazy val module = new BoomRocketTopWithPWMAXI4Module(this)
|
||||
override lazy val module = new TopWithPWMAXI4Module(this)
|
||||
}
|
||||
|
||||
class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l)
|
||||
class TopWithPWMAXI4Module(l: TopWithPWMAXI4) extends TopModule(l)
|
||||
with HasPeripheryPWMAXI4ModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop
|
||||
class TopWithBlockDevice(implicit p: Parameters) extends Top
|
||||
with HasPeripheryBlockDevice {
|
||||
override lazy val module = new BoomRocketTopWithBlockDeviceModule(this)
|
||||
override lazy val module = new TopWithBlockDeviceModule(this)
|
||||
}
|
||||
|
||||
class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l)
|
||||
class TopWithBlockDeviceModule(l: TopWithBlockDevice) extends TopModule(l)
|
||||
with HasPeripheryBlockDeviceModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop
|
||||
with HasPeripheryGPIO {
|
||||
override lazy val module = new BoomRocketTopWithGPIOModule(this)
|
||||
class TopWithGPIO(implicit p: Parameters) extends Top
|
||||
with HasPeripheryGPIO {
|
||||
override lazy val module = new TopWithGPIOModule(this)
|
||||
}
|
||||
|
||||
class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO)
|
||||
extends BoomRocketTopModule(l)
|
||||
class TopWithGPIOModule(l: TopWithGPIO)
|
||||
extends TopModule(l)
|
||||
with HasPeripheryGPIOModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem
|
||||
class TopWithDTM(implicit p: Parameters) extends System
|
||||
{
|
||||
override lazy val module = new BoomRocketTopWithDTMModule(this)
|
||||
override lazy val module = new TopWithDTMModule(this)
|
||||
}
|
||||
|
||||
class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l)
|
||||
class TopWithDTMModule[+L <: TopWithDTM](l: L) extends SystemModule(l)
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ import freechips.rocketchip.config.{Parameters}
|
|||
import freechips.rocketchip.util.{GeneratorApp}
|
||||
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
|
||||
|
||||
import boom.system.{BoomTilesKey}
|
||||
import boom.common.{BoomTilesKey}
|
||||
|
||||
/**
|
||||
* A set of pre-chosen regression tests
|
||||
|
|
|
|||
|
|
@ -32,11 +32,11 @@ ifeq ($(SUB_PROJECT),example)
|
|||
MODEL ?= TestHarness
|
||||
VLOG_MODEL ?= TestHarness
|
||||
MODEL_PACKAGE ?= $(SBT_PROJECT)
|
||||
CONFIG ?= DefaultRocketConfig
|
||||
CONFIG ?= RocketConfig
|
||||
CONFIG_PACKAGE ?= $(SBT_PROJECT)
|
||||
GENERATOR_PACKAGE ?= $(SBT_PROJECT)
|
||||
TB ?= TestDriver
|
||||
TOP ?= BoomRocketTop
|
||||
TOP ?= Top
|
||||
endif
|
||||
# for Rocket-chip developers
|
||||
ifeq ($(SUB_PROJECT),rocketchip)
|
||||
|
|
|
|||
Loading…
Reference in New Issue