lowercase readme

This commit is contained in:
abejgonzalez 2019-04-18 20:10:20 -07:00
parent eec137e1ee
commit daed74b873
1 changed files with 3 additions and 3 deletions

View File

@ -1,8 +1,8 @@
# RISC-V Project Template
**THIS BRANCH IS UNDER DEVELOPMENT**
**IT CURRENTLY HAS MANY SUBMODULES**
**PLEASE RUN ./scripts/init-submodules-no-riscv-tools.sh TO UPDATE SUBMODULES, UNLESS YOU WANT TO SPEND A LONG TIME WAITING FOR SUBMODULE TO CLONE**
**This branch is under development**
**It currently has many submodules**
**Please run ./scripts/init-submodules-no-riscv-tools.sh to update submodules, unless you want to spend a long time waiting for submodule to clone**
This is a starter template for your custom RISC-V project. It will allow you
to leverage the Chisel HDL and RocketChip SoC generator to produce a