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@ -11,7 +11,7 @@ Chipyard aims to be the "one-stop shop" for creating and testing your own unique
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Chisel/FIRRTL
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-------------------------------------------
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One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language <https://chisel.eecs.berkeley.edu/>`__ and the `FIRRTL Compiler <https://freechipsproject.github.io/firrtl/>`__.
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One of the tools to help create new RTL designs quickly is the `Chisel Hardware Construction Language <https://chisel-lang.org/>`__ and the `FIRRTL Compiler <https://chisel-lang.org/firrtl/>`__.
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Chisel is an embedded language within Scala that provides a set of libraries to help hardware designers create highly parameterizable RTL.
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FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more!
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These two tools in combination allow quick design space exploration and development of new RTL.
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@ -1,7 +1,7 @@
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Chisel
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===========================
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`Chisel <https://chisel.eecs.berkeley.edu/>`__ is an open-source hardware description language embedded in Scala.
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`Chisel <https://chisel-lang.org/>`__ is an open-source hardware description language embedded in Scala.
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It supports advanced hardware design using highly parameterized generators and supports things such as Rocket Chip and BOOM.
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After writing Chisel, there are multiple steps before the Chisel source code "turns into" Verilog.
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@ -16,4 +16,4 @@ However, if that passes, the output of the generator gives you an FIRRTL file an
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See :ref:`FIRRTL` for more information on how to get a FIRRTL file to Verilog.
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For an interactive tutorial on how to use Chisel and get started please visit the `Chisel Bootcamp <https://github.com/freechipsproject/chisel-bootcamp>`__.
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Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel.eecs.berkeley.edu/>`__.
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Otherwise, for all things Chisel related including API documentation, news, etc, visit their `website <https://chisel-lang.org/>`__.
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@ -8,6 +8,4 @@ Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (ano
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An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
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Once the transformations are done, a Verilog file is emitted and the build process is done.
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For more information on please visit their `website <https://freechipsproject.github.io/firrtl/>`__.
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For more information on please visit their `website <https://chisel-lang.org/firrtl/>`__.
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