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Update vlsi/Makefile to match variables.mk naming

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Jerry Zhao 2019-07-18 17:45:13 -07:00 committed by GitHub
parent 7a55b74ed2
commit b76e896598
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1 changed files with 1 additions and 1 deletions
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vlsi/Makefile
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@ -44,7 +44,7 @@ ROCKET_SRCS = \
$(ROCKET_SRC_DIR)/plusarg_reader.v \
$(ROCKET_SRC_DIR)/EICG_wrapper.v \
ALL_RTL = $(ROCKET_SRCS) $(VERILOG_FILE) $(SMEMS_FILE)
ALL_RTL = $(ROCKET_SRCS) $(TOP_FILE) $(TOP_SMEMS_FILE)
CLOCK_DOMAINS = $(build_dir)/$(long_name).domains