diff --git a/common.mk b/common.mk index c59d38b..cf79fb2 100644 --- a/common.mk +++ b/common.mk @@ -47,13 +47,14 @@ $(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf) # create verilog files rules and variables ######################################################################################### REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF) +HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF) $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)" cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes) $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes) - cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)" + cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)" grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes) # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs @@ -61,6 +62,10 @@ MACROCOMPILER_MODE ?= --mode synflops $(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF) cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)" +HARNESS_MACROCOMPILER_MODE = --mode synflops +$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF) + cd $(base_dir) && $(SBT) "project barstools-macros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" + ######################################################################################### # helper rule to just make verilog files ######################################################################################### diff --git a/generators/rocket-chip b/generators/rocket-chip index a05728c..b8baef6 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit a05728c4fab84a13585e14ac684b47c875b17b57 +Subproject commit b8baef6f26fa36c9b4e0b2a5eec12cd76ae5daf8 diff --git a/toolchains/riscv-tools b/toolchains/riscv-tools index 962bc09..bce7b5e 160000 --- a/toolchains/riscv-tools +++ b/toolchains/riscv-tools @@ -1 +1 @@ -Subproject commit 962bc09873071aa7816d5f805c6e5797a3b5bcf7 +Subproject commit bce7b5e363957c134f944769e677354467b7e4ed diff --git a/tools/barstools b/tools/barstools index e548210..9193c67 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit e548210ef42e634e75cf283292685728114694c6 +Subproject commit 9193c67ec916c76414a4e72a1ce84e9ffb8accec diff --git a/tools/chisel3 b/tools/chisel3 index 9a0ce22..e1aa5f3 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit 9a0ce2272c9d5d0a8bdc90e84269749ce054664d +Subproject commit e1aa5f3f5c0cdeb204047c3ca50801d9f7ea25f1 diff --git a/tools/firrtl b/tools/firrtl index bf66997..99ae1d6 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit bf66997b1a2438a322cd619ca2b6aeb0f0ac0ba0 +Subproject commit 99ae1d6649f1731c5dec2098b10733735232b72c diff --git a/variables.mk b/variables.mk index 9470924..611f1dd 100644 --- a/variables.mk +++ b/variables.mk @@ -107,20 +107,23 @@ ifeq ($(GENERATOR_PACKAGE),hwacha) long_name=$(MODEL_PACKAGE).$(CONFIG) endif -FIRRTL_FILE ?= $(build_dir)/$(long_name).fir -ANNO_FILE ?= $(build_dir)/$(long_name).anno.json -VERILOG_FILE ?= $(build_dir)/$(long_name).top.v -TOP_FIR ?= $(build_dir)/$(long_name).top.fir -TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json -HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v -HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir -HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json -SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v -SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf -SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir -sim_dotf ?= $(build_dir)/sim_files.f +FIRRTL_FILE ?= $(build_dir)/$(long_name).fir +ANNO_FILE ?= $(build_dir)/$(long_name).anno.json +VERILOG_FILE ?= $(build_dir)/$(long_name).top.v +TOP_FIR ?= $(build_dir)/$(long_name).top.fir +TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json +HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v +HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir +HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json +HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v +HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf +HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir +SMEMS_FILE ?= $(build_dir)/$(long_name).mems.v +SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf +SMEMS_FIR ?= $(build_dir)/$(long_name).mems.fir +sim_dotf ?= $(build_dir)/sim_files.f sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f -sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f +sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f ######################################################################################### # java arguments used in sbt @@ -157,7 +160,8 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc sim_vsrcs = \ $(VERILOG_FILE) \ $(HARNESS_FILE) \ - $(SMEMS_FILE) + $(SMEMS_FILE) \ + $(HARNESS_SMEMS_FILE) ######################################################################################### # assembly/benchmark variables