smaller rocket For hwacha ci
This commit is contained in:
parent
1226591231
commit
a377c520a6
|
@ -255,7 +255,7 @@ jobs:
|
|||
|
||||
- run:
|
||||
name: Building the hwacha subproject using Verilator
|
||||
command: .circleci/do-rtl-build.sh SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallHwachaConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem
|
||||
command: .circleci/do-rtl-build.sh SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallRocketForHwachaCIConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem
|
||||
no_output_timeout: 120m
|
||||
|
||||
- save_cache:
|
||||
|
@ -401,7 +401,7 @@ jobs:
|
|||
|
||||
- run:
|
||||
name: Run hwacha benchmark tests
|
||||
command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallHwachaConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem
|
||||
command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallRocketForHwachaCIConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem
|
||||
|
||||
# Order and dependencies of jobs to run
|
||||
workflows:
|
||||
|
|
|
@ -2,10 +2,11 @@ package example
|
|||
|
||||
import chisel3._
|
||||
import freechips.rocketchip.config.{Parameters, Config}
|
||||
import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
|
||||
import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, CacheBlockBytes, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
|
||||
import freechips.rocketchip.diplomacy.{LazyModule, ValName}
|
||||
import freechips.rocketchip.devices.tilelink.BootROMParams
|
||||
import freechips.rocketchip.tile.XLen
|
||||
import freechips.rocketchip.tile.{XLen, RocketTileParams}
|
||||
import freechips.rocketchip.rocket.{RocketCoreParams, DCacheParams, ICacheParams, MulDivParams}
|
||||
import testchipip._
|
||||
import sifive.blocks.devices.gpio._
|
||||
|
||||
|
@ -168,3 +169,35 @@ class WithGPIOBoomTop extends Config((site, here, up) => {
|
|||
top
|
||||
}
|
||||
})
|
||||
|
||||
// -------------
|
||||
// Mixins for CI
|
||||
// -------------
|
||||
|
||||
/**
|
||||
* Class to specify a smaller Rocket core for Hwacha CI
|
||||
*/
|
||||
class WithNHwachaSmallCores(n: Int) extends Config((site, here, up) => {
|
||||
case RocketTilesKey => {
|
||||
val small = RocketTileParams(
|
||||
core = RocketCoreParams(mulDiv = Some(MulDivParams(
|
||||
mulUnroll = 8,
|
||||
mulEarlyOut = true,
|
||||
divEarlyOut = true))),
|
||||
btb = None,
|
||||
dcache = Some(DCacheParams(
|
||||
rowBits = site(SystemBusKey).beatBits,
|
||||
nSets = 32,
|
||||
nWays = 1,
|
||||
nTLBEntries = 4,
|
||||
nMSHRs = 0,
|
||||
blockBytes = site(CacheBlockBytes))),
|
||||
icache = Some(ICacheParams(
|
||||
rowBits = site(SystemBusKey).beatBits,
|
||||
nSets = 32,
|
||||
nWays = 1,
|
||||
nTLBEntries = 4,
|
||||
blockBytes = site(CacheBlockBytes))))
|
||||
List.tabulate(n)(i => small.copy(hartId = i))
|
||||
}
|
||||
})
|
||||
|
|
|
@ -21,10 +21,11 @@ class HwachaConfig extends Config(
|
|||
new hwacha.DefaultHwachaConfig ++
|
||||
new DefaultRocketConfig)
|
||||
|
||||
class SmallHwachaConfig extends Config(
|
||||
class SmallRocketForHwachaCIConfig extends Config(
|
||||
new WithNBanks(1) ++
|
||||
new WithNHwachaSmallCores(1) ++
|
||||
new hwacha.DefaultHwachaConfig ++
|
||||
new freechips.rocketchip.system.DefaultConfig)
|
||||
new DefaultRocketConfig)
|
||||
|
||||
class RoccRocketConfig extends Config(
|
||||
new WithRoccExample ++
|
||||
|
|
Loading…
Reference in New Issue