Fix Config comments

This commit is contained in:
Jerry Zhao 2019-08-26 16:31:10 -07:00
parent 93c3a2cd72
commit 939ce4ea17
2 changed files with 10 additions and 10 deletions

View File

@ -11,10 +11,10 @@ import freechips.rocketchip.config.{Config}
class SmallBoomConfig extends Config(
new WithTop ++ // use normal top
new WithBootROM ++ // use testchipip bootrom
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive L2 cache
new boom.common.WithSmallBooms ++ // 1-wide BOOM
new boom.common.WithNBoomCores(1) ++ // single-core
new freechips.rocketchip.system.BaseConfig) // "Base" rocketchip system
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class MediumBoomConfig extends Config(
new WithTop ++

View File

@ -9,14 +9,14 @@ import freechips.rocketchip.config.{Config}
// ---------------------
class LargeBoomAndRocketConfig extends Config(
new WithTop ++ // default top
new WithBootROM ++ // default bootrom
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive l2
new boom.common.WithRenumberHarts ++ // avoid hartid overlap
new boom.common.WithLargeBooms ++ // 3-wide boom
new boom.common.WithNBoomCores(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket
new freechips.rocketchip.system.BaseConfig) // "Base" rocketchip system
new WithTop ++ // default top
new WithBootROM ++ // default bootrom
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2
new boom.common.WithRenumberHarts ++ // avoid hartid overlap
new boom.common.WithLargeBooms ++ // 3-wide boom
new boom.common.WithNBoomCores(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new WithTop ++