Fix Config comments
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@ -11,10 +11,10 @@ import freechips.rocketchip.config.{Config}
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class SmallBoomConfig extends Config(
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new WithTop ++ // use normal top
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new WithBootROM ++ // use testchipip bootrom
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive L2 cache
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new boom.common.WithSmallBooms ++ // 1-wide BOOM
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new boom.common.WithNBoomCores(1) ++ // single-core
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new freechips.rocketchip.system.BaseConfig) // "Base" rocketchip system
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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class MediumBoomConfig extends Config(
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new WithTop ++
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@ -9,14 +9,14 @@ import freechips.rocketchip.config.{Config}
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// ---------------------
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class LargeBoomAndRocketConfig extends Config(
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new WithTop ++ // default top
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new WithBootROM ++ // default bootrom
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive l2
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new boom.common.WithRenumberHarts ++ // avoid hartid overlap
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new boom.common.WithLargeBooms ++ // 3-wide boom
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new boom.common.WithNBoomCores(1) ++ // single-core boom
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket
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new freechips.rocketchip.system.BaseConfig) // "Base" rocketchip system
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new WithTop ++ // default top
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new WithBootROM ++ // default bootrom
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2
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new boom.common.WithRenumberHarts ++ // avoid hartid overlap
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new boom.common.WithLargeBooms ++ // 3-wide boom
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new boom.common.WithNBoomCores(1) ++ // single-core boom
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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class HwachaLargeBoomAndHwachaRocketConfig extends Config(
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new WithTop ++
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