From ee75c03875515095e14506b545a0862856f6e47d Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Fri, 2 Aug 2019 15:09:22 -0700 Subject: [PATCH 1/2] Add dsptools. --- .gitmodules | 9 +++++++ build.sbt | 57 +++++++++++++++++++++++++++++++++++++------- tools/chisel-testers | 1 + tools/dsptools | 1 + tools/treadle | 1 + 5 files changed, 61 insertions(+), 8 deletions(-) create mode 160000 tools/chisel-testers create mode 160000 tools/dsptools create mode 160000 tools/treadle diff --git a/.gitmodules b/.gitmodules index 5bbbedd..2684698 100644 --- a/.gitmodules +++ b/.gitmodules @@ -46,3 +46,12 @@ [submodule "vlsi/hammer-cad-plugins"] path = vlsi/hammer-cad-plugins url = https://github.com/ucb-bar/hammer-cad-plugins.git +[submodule "tools/dsptools"] + path = tools/dsptools + url = https://github.com/ucb-bar/dsptools.git +[submodule "tools/chisel-testers"] + path = tools/chisel-testers + url = https://github.com/freechipsproject/chisel-testers.git +[submodule "tools/treadle"] + path = tools/treadle + url = https://github.com/freechipsproject/treadle.git diff --git a/build.sbt b/build.sbt index cb3a0b6..c5562c4 100644 --- a/build.sbt +++ b/build.sbt @@ -43,6 +43,22 @@ def conditionalDependsOn(prj: Project): Project = { } } +/** + * It has been a struggle for us to override settings in subprojects. + * An example would be adding a dependency to rocketchip on midas's targetutils library, + * or replacing dsptools's maven dependency on chisel with the local chisel project. + * + * This function works around this by specifying the project's root at src/ and overriding + * scalaSource and resourceDirectory. + */ +def freshProject(name: String, dir: File): Project = { + Project(id = name, base = dir / "src") + .settings( + scalaSource in Compile := baseDirectory.value / "main" / "scala", + resourceDirectory in Compile := baseDirectory.value / "main" / "resources" + ) +} + // Fork each scala test for now, to work around persistent mutable state // in Rocket-Chip based generators def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => @@ -55,6 +71,21 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test => // NB: FIRRTL dependency is unmanaged (and dropped in sim/lib) lazy val chisel = (project in rocketChipDir / "chisel3") +lazy val treadle = freshProject("treadle", file("tools/treadle")) + .settings(commonSettings) + +lazy val `chisel-testers` = freshProject("chisel-testers", file("./tools/chisel-testers")) + .dependsOn(treadle, chisel) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "junit" % "junit" % "4.12", + "org.scalatest" %% "scalatest" % "3.0.5", + "org.scalacheck" %% "scalacheck" % "1.14.0", + "com.github.scopt" %% "scopt" % "3.7.0" + ) + ) + // Contains annotations & firrtl passes you may wish to use in rocket-chip without // introducing a circular dependency between RC and MIDAS lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils") @@ -66,14 +97,8 @@ lazy val hardfloat = (project in rocketChipDir / "hardfloat") lazy val rocketMacros = (project in rocketChipDir / "macros") .settings(commonSettings) -// HACK: I'm strugging to override settings in rocket-chip's build.sbt (i want -// the subproject to register a new library dependendency on midas's targetutils library) -// So instead, avoid the existing build.sbt altogether and specify the project's root at src/ -lazy val rocketchip = (project in rocketChipDir / "src") - .settings( - commonSettings, - scalaSource in Compile := baseDirectory.value / "main" / "scala", - resourceDirectory in Compile := baseDirectory.value / "main" / "resources") +lazy val rocketchip = freshProject("rocketchip", rocketChipDir) + .settings(commonSettings) .dependsOn(chisel, hardfloat, rocketMacros) lazy val testchipip = (project in file("generators/testchipip")) @@ -110,6 +135,22 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/")) .enablePlugins(sbtassembly.AssemblyPlugin) .settings(commonSettings) +lazy val dsptools = freshProject("dsptools", file("./tools/dsptools")) + .dependsOn(chisel, `chisel-testers`) + .settings( + commonSettings, + libraryDependencies ++= Seq( + "org.typelevel" %% "spire" % "0.14.1", + "org.scalanlp" %% "breeze" % "0.13.2", + "junit" % "junit" % "4.12" % "test", + "org.scalatest" %% "scalatest" % "3.0.5" % "test", + "org.scalacheck" %% "scalacheck" % "1.14.0" % "test" + )) + +lazy val `rocket-dsptools` = (project in file("./tools/dsptools/rocket")) + .dependsOn(rocketchip, dsptools) + .settings(commonSettings) + lazy val sifive_blocks = (project in file("generators/sifive-blocks")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/tools/chisel-testers b/tools/chisel-testers new file mode 160000 index 0000000..41f4eef --- /dev/null +++ b/tools/chisel-testers @@ -0,0 +1 @@ +Subproject commit 41f4eef0d85b65fabd0d786efa8baa099513dcf0 diff --git a/tools/dsptools b/tools/dsptools new file mode 160000 index 0000000..15145ab --- /dev/null +++ b/tools/dsptools @@ -0,0 +1 @@ +Subproject commit 15145ab6230f869676de7eb730b4267fff7b11e8 diff --git a/tools/treadle b/tools/treadle new file mode 160000 index 0000000..a03b969 --- /dev/null +++ b/tools/treadle @@ -0,0 +1 @@ +Subproject commit a03b969af104770a7662ecdbac80cebf622e674b From af3cb7cf1991cb940c75d14c23b96e6cf0b45dab Mon Sep 17 00:00:00 2001 From: Paul Rigge Date: Fri, 2 Aug 2019 23:21:59 -0700 Subject: [PATCH 2/2] Add some documentation for dsptools et al --- docs/Tools/Chisel-Testers.rst | 6 ++++++ docs/Tools/Dsptools.rst | 15 +++++++++++++++ docs/Tools/Treadle.rst | 5 +++++ docs/Tools/index.rst | 3 +++ 4 files changed, 29 insertions(+) create mode 100644 docs/Tools/Chisel-Testers.rst create mode 100644 docs/Tools/Dsptools.rst create mode 100644 docs/Tools/Treadle.rst diff --git a/docs/Tools/Chisel-Testers.rst b/docs/Tools/Chisel-Testers.rst new file mode 100644 index 0000000..7a9ebf2 --- /dev/null +++ b/docs/Tools/Chisel-Testers.rst @@ -0,0 +1,6 @@ +Chisel Testers +============================== + +`Chisel testers `__ is a library for writing tests for Chisel designs. +It provides a Scala API for interacting with a DUT. +It can use multiple backends, including :ref:`Treadle` and Verilator. diff --git a/docs/Tools/Dsptools.rst b/docs/Tools/Dsptools.rst new file mode 100644 index 0000000..ed946b5 --- /dev/null +++ b/docs/Tools/Dsptools.rst @@ -0,0 +1,15 @@ +Dsptools +=============================== + +`Dsptools `__ is a Chisel library for writing custom signal processing hardware. +Additionally, dsptools is useful for integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). + +Some features: + +* Complex type +* Typeclasses for writing polymorphic hardware generators + * For example, write one FIR filter generator that works for real or complex inputs +* Extensions to Chisel testers for fixed point and floating point types +* A diplomatic implementation of AXI4-Stream +* Models for verifying APB, AXI-4, and TileLink interfaces with chisel-testers +* DSP building blocks diff --git a/docs/Tools/Treadle.rst b/docs/Tools/Treadle.rst new file mode 100644 index 0000000..19df75d --- /dev/null +++ b/docs/Tools/Treadle.rst @@ -0,0 +1,5 @@ +Treadle +============================== + +`Treadle `__ is a circuit simulator that directly executes FIRRTL. +It is especially useful for interactive debugging and small unit tests that benefit from a low-overhead simulator. diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index d73d407..efe38e3 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -10,5 +10,8 @@ The following pages will introduce them, and how we can use them in order to gen Chisel FIRRTL + Treadle + Chisel-Testers + Dsptools Barstools