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Use HasHierarchicalBusTopology mixin

This commit is contained in:
Jerry Zhao 2019-08-27 12:00:50 -07:00
parent 65003f86d0
commit 1d85dc32a0
1 changed files with 1 additions and 19 deletions
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20
generators/example/src/main/scala/System.scala
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@ -22,6 +22,7 @@ import freechips.rocketchip.util.{DontTouch}
* Base top with periphery devices and ports, and a BOOM + Rocket subsystem * Base top with periphery devices and ports, and a BOOM + Rocket subsystem
*/ */
class System(implicit p: Parameters) extends Subsystem class System(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology
with HasAsyncExtInterrupts with HasAsyncExtInterrupts
with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MemPort
with CanHaveMasterAXI4MMIOPort with CanHaveMasterAXI4MMIOPort
@ -29,25 +30,6 @@ class System(implicit p: Parameters) extends Subsystem
with HasPeripheryBootROM with HasPeripheryBootROM
{ {
override lazy val module = new SystemModule(this) override lazy val module = new SystemModule(this)
// The sbus masters the cbus; here we convert TL-UH -> TL-UL
sbus.crossToBus(cbus, NoCrossing)
// The cbus masters the pbus; which might be clocked slower
cbus.crossToBus(pbus, SynchronousCrossing())
// The fbus masters the sbus; both are TL-UH or TL-C
FlipRendering { implicit p =>
sbus.crossFromBus(fbus, SynchronousCrossing())
}
// The sbus masters the mbus; here we convert TL-C -> TL-UH
private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
private val (in, out, halt) = coherenceManager(this)
if (nBanks != 0) {
sbus.coupleTo("coherence_manager") { in :*= _ }
mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
}
} }
/** /**