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[FireChip] Update BOOM based targets to use new SubSystem

This commit is contained in:
David Biancolin 2019-06-28 18:49:03 +00:00
parent 1bd9b08717
commit 0faadb75d6
3 changed files with 5 additions and 6 deletions
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0
generators/firechip/src/main/scala/Generator.scala Executable file → Normal file
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1
generators/firechip/src/main/scala/TargetMixins.scala
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@ -10,7 +10,6 @@ import freechips.rocketchip.util._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.TracedInstruction
import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
import boom.system.BoomSubsystem
import midas.models.AXI4BundleWithEdge
import midas.targetutils.ExcludeInstanceAsserts

10
generators/firechip/src/main/scala/Targets.scala Executable file → Normal file
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@ -11,7 +11,7 @@ import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.amba.axi4.AXI4Bundle
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.LazyModule
import boom.system.{BoomSubsystem, BoomSubsystemModuleImp}
import boom.system.{BoomRocketSubsystem, BoomRocketSubsystemModuleImp}
import icenet._
import testchipip._
import testchipip.SerialAdapter.SERIAL_IF_WIDTH
@ -80,7 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
with HasTraceIOImp
class FireBoom(implicit p: Parameters) extends BoomSubsystem
class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem
with HasDefaultBusConfiguration
with CanHaveFASEDOptimizedMasterAXI4MemPort
with HasPeripheryBootROM
@ -94,7 +94,7 @@ class FireBoom(implicit p: Parameters) extends BoomSubsystem
override lazy val module = new FireBoomModuleImp(this)
}
class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomSubsystemModuleImp(l)
class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp
@ -106,7 +106,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomSubsystemModuleImp(l)
with HasTraceIOImp
with ExcludeInvalidBoomAssertions
class FireBoomNoNIC(implicit p: Parameters) extends BoomSubsystem
class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem
with HasDefaultBusConfiguration
with CanHaveFASEDOptimizedMasterAXI4MemPort
with HasPeripheryBootROM
@ -119,7 +119,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomSubsystem
override lazy val module = new FireBoomNoNICModuleImp(this)
}
class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomSubsystemModuleImp(l)
class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsystemModuleImp(l)
with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp