diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index d0be57c..63f4750 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -14,5 +14,5 @@ if [ ! -d "$HOME/$1-install" ]; then cd $HOME # init all submodules including the tools - CHIPYARD_DIR=$LOCAL_CHIPYARD_DIR .$LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 + CHIPYARD_DIR=$LOCAL_CHIPYARD_DIR $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 fi diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 630bbd0..a282ebf 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -13,6 +13,7 @@ source $SCRIPT_DIR/defaults.sh cd $LOCAL_CHIPYARD_DIR # initialize submodules and get the hashes +git config submodule.vlsi/hammer-cad-plugins.update none git submodule update --init status=$(git submodule status) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e777af6..25b365d 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -41,4 +41,4 @@ mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketCon mapping["boom"]="SUB_PROJECT=boom" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice" -mapping["hwacha"]="SUB_PROJECT=hwacha" +mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaL2Config GENERATOR_PACKAGE=hwacha" diff --git a/.gitignore b/.gitignore index 8450e9b..08493ee 100644 --- a/.gitignore +++ b/.gitignore @@ -10,3 +10,4 @@ target env.sh riscv-tools-install tags +*~ \ No newline at end of file diff --git a/.gitmodules b/.gitmodules index ca80d66..5bbbedd 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,12 +13,6 @@ [submodule "tools/firrtl"] path = tools/firrtl url = https://github.com/freechipsproject/firrtl -[submodule "riscv-tools"] - path = toolchains/riscv-tools - url = https://github.com/riscv/riscv-tools.git -[submodule "esp-tools"] - path = toolchains/esp-tools - url = https://github.com/ucb-bar/esp-tools.git [submodule "tools/torture"] path = tools/torture url = https://github.com/ucb-bar/riscv-torture.git @@ -40,3 +34,15 @@ [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache url = https://github.com/sifive/block-inclusivecache-sifive.git +[submodule "toolchains/riscv-tools"] + path = toolchains/riscv-tools + url = https://github.com/freechipsproject/rocket-tools.git +[submodule "toolchains/esp-tools"] + path = toolchains/esp-tools + url = https://github.com/ucb-bar/esp-tools.git +[submodule "vlsi/hammer"] + path = vlsi/hammer + url = https://github.com/ucb-bar/hammer.git +[submodule "vlsi/hammer-cad-plugins"] + path = vlsi/hammer-cad-plugins + url = https://github.com/ucb-bar/hammer-cad-plugins.git diff --git a/common.mk b/common.mk index fe0cb02..f9d5896 100644 --- a/common.mk +++ b/common.mk @@ -82,7 +82,7 @@ verilog: $(sim_vsrcs) ######################################################################################### # helper rules to run simulations ######################################################################################### -.PHONY: run-binary run-fast +.PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 3>&1 1>&2 2>&3 | spike-dasm > $(sim_out_name).out) diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index c2334ca..c6cfa7a 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -63,7 +63,13 @@ class GB1MemoryConfig extends Config( new DefaultRocketConfig) class RocketL2Config extends Config( - new WithInclusiveCache ++ new DefaultRocketConfig) + new WithInclusiveCache ++ + new DefaultRocketConfig) + +class HwachaL2Config extends Config( + new hwacha.DefaultHwachaConfig ++ + new WithInclusiveCache ++ + new DefaultRocketConfig) // ------------ // BOOM Configs @@ -146,7 +152,8 @@ class RV32UnifiedBoomConfig extends Config( new boom.system.SmallRV32UnifiedBoomConfig) class BoomL2Config extends Config( - new WithInclusiveCache ++ new SmallDefaultBoomConfig) + new WithInclusiveCache ++ + new SmallDefaultBoomConfig) // --------------------- // BOOM and Rocket Configs @@ -255,4 +262,5 @@ class RV32BoomAndRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) class DualCoreRocketL2Config extends Config( - new WithInclusiveCache ++ new DualCoreRocketConfig) + new WithInclusiveCache ++ + new DualCoreRocketConfig) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 5544376..7b4d5d4 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -14,30 +14,6 @@ import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} import midas.models.AXI4BundleWithEdge import midas.targetutils.ExcludeInstanceAsserts -/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ -trait HasDefaultBusConfiguration { - this: BaseSubsystem => - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } -} - - /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges * associated with each port. This drives FASED functional model sizing */ diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index c907704..7f8bb83 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -31,7 +31,7 @@ import java.io.File *******************************************************************************/ class FireSim(implicit p: Parameters) extends RocketSubsystem - with HasDefaultBusConfiguration + with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -57,7 +57,7 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem - with HasDefaultBusConfiguration + with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -81,7 +81,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem - with HasDefaultBusConfiguration + with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -107,7 +107,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI with ExcludeInvalidBoomAssertions class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem - with HasDefaultBusConfiguration + with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug diff --git a/scripts/build-static-libfesvr.sh b/scripts/build-static-libfesvr.sh new file mode 100755 index 0000000..360028a --- /dev/null +++ b/scripts/build-static-libfesvr.sh @@ -0,0 +1,17 @@ +#!/usr/bin/env bash + +# This ungodly script surreptitiously builds an archive from existing fesvr objects +# Invoke from riscv-fesvr/build + +if [ "x$RISCV" = "x" ] +then + echo "Please set the RISCV environment variable to your preferred install path." + exit 1 +fi + +set -e + +objs=$(head -n 1 <(make -f <( echo -e 'include Makefile\n$(info $(value fesvr_objs))') -n)) +ar rcs -o libfesvr.a $objs +cp -f libfesvr.a $RISCV/lib + diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 20ce480..ac4316b 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -1,5 +1,7 @@ #!/usr/bin/env bash +#this script is based on the firesim build toolchains script + # exit script if any command fails set -e set -o pipefail @@ -8,31 +10,151 @@ unamestr=$(uname) RDIR=$(pwd) : ${CHIPYARD_DIR:=$(pwd)} #default value is the PWD unless overridden -if [ $# -ne 0 ]; then - TOOLCHAIN=$1 - if [ $1 == "riscv" ]; then - TOOLCHAIN="riscv-tools" - elif [ $1 == "hwacha" ]; then - TOOLCHAIN="esp-tools" - fi -else - TOOLCHAIN="riscv-tools" +PRECOMPILED_REPO_HASH=56a40961c98db5e8f904f15dc6efd0870bfefd9e + +function usage +{ + echo "usage: ./scripts/build-toolchains.sh [riscv-tools] [esp-tools] [ec2fast | --ec2fast] " + echo " riscv: if set, builds the riscv toolchain (this is also the default)" + echo " hwacha: if set, builds esp-tools toolchain" + echo " ec2fast: if set, pulls in a pre-compiled RISC-V toolchain for an EC2 manager instance" +} + +#taken from riscv-tools to check for open-ocd autoconf versions +check_version() { + $1 --version | awk "NR==1 {if (\$NF>$2) {exit 0} exit 1}" || ( + echo $3 requires at least version $2 of $1. Aborting. + exit 1 + ) +} + +if [ "$1" == "--help" -o "$1" == "-h" -o "$1" == "-H" ]; then + usage + exit 3 +fi + +TOOLCHAIN="riscv-tools" +EC2FASTINSTALL="false" +FASTINSTALL="false" +while test $# -gt 0 +do + case "$1" in + riscv-tools) + TOOLCHAIN="riscv-tools" + ;; + esp-tools) + TOOLCHAIN="esp-tools" + ;; + ec2fast | --ec2fast) # I don't want to break this api + EC2FASTINSTALL=true + ;; + -h | -H | --help) + usage + exit 3 + ;; + --*) echo "ERROR: bad option $1" + usage + exit 1 + ;; + *) echo "ERROR: bad argument $1" + usage + exit 2 + ;; + esac + shift +done + + +if [ "$EC2FASTINSTALL" = "true" ]; then + if [ "$TOOLCHAIN" = "riscv-tools" ]; then + cd $RDIR + git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git + cd firesim-riscv-tools-prebuilt + git checkout $PRECOMPILED_REPO_HASH + PREBUILTHASH="$(cat HASH)" + git -C $CHIPYARD_DIR submodule update --init toolchains/$TOOLCHAIN + cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" + GITHASH="$(git rev-parse HEAD)" + cd $RDIR + echo "prebuilt hash: $PREBUILTHASH" + echo "git hash: $GITHASH" + if [[ $PREBUILTHASH == $GITHASH && "$EC2FASTINSTALL" == "true" ]]; then + FASTINSTALL=true + echo "Using fast pre-compiled install for riscv-tools" + else + echo "Error: hash of precompiled toolchain doesn't match the riscv-tools submodule hash." + exit + fi + else + echo "Error: No precompiled toolchain for esp-tools or other non-native riscv-tools." + exit + fi fi INSTALL_DIR="$TOOLCHAIN-install" -mkdir -p "$(pwd)/$INSTALL_DIR" RISCV="$(pwd)/$INSTALL_DIR" # install risc-v tools export RISCV="$RISCV" -git -C $CHIPYARD_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 -cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" -export MAKEFLAGS="-j16" -./build.sh + +if [ "$FASTINSTALL" = true ]; then + cd firesim-riscv-tools-prebuilt + ./installrelease.sh + mv distrib "$RISCV" + # copy HASH in case user wants it later + cp HASH "$RISCV" + cd $RDIR + rm -rf firesim-riscv-tools-prebuilt +else + mkdir -p "$RISCV" + git -C $CHIPYARD_DIR submodule update --init --recursive toolchains/$TOOLCHAIN #--jobs 8 + cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" + export MAKEFLAGS="-j16" + #build the actual toolchain + #./build.sh + source build.common + echo "Starting RISC-V Toolchain build process" + build_project riscv-fesvr --prefix=$RISCV + build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV + build_project riscv-gnu-toolchain --prefix=$RISCV + CC= CXX= build_project riscv-pk --prefix=$RISCV --host=riscv64-unknown-elf + build_project riscv-tests --prefix=$RISCV/riscv64-unknown-elf + echo -e "\\nRISC-V Toolchain installation completed!" + + # build static libfesvr library for linking into firesim driver (or others) + cd riscv-fesvr/build + $CHIPYARD_DIR/scripts/build-static-libfesvr.sh + cd $RDIR + # build linux toolchain + cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN/riscv-gnu-toolchain/build" + make -j16 linux + echo -e "\\nRISC-V Linux GNU Toolchain installation completed!" + +fi + cd $RDIR -echo "export RISCV=$RISCV" > env.sh +echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" > env.sh +echo "export RISCV=$RISCV" >> env.sh echo "export PATH=$RISCV/bin:$RDIR/$DTCversion:\$PATH" >> env.sh echo "export LD_LIBRARY_PATH=$RISCV/lib" >> env.sh echo "Toolchain Build Complete!" + + +if [ "$FASTINSTALL" = "false" ]; then + # commands that can't run on EC2 (specifically, OpenOCD because of autoconf version_ + # see if the instance info page exists. if not, we are not on ec2. + # this is one of the few methods that works without sudo + if wget -T 1 -t 3 -O /dev/null http://169.254.169.254/; then + echo "Skipping RISC-V OpenOCD" + else + echo "Building RISC-V OpenOCD" + cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" + check_version automake 1.14 "OpenOCD build" + check_version autoconf 2.64 "OpenOCD build" + build_project riscv-openocd --prefix=$RISCV --enable-remote-bitbang --enable-jtag_vpi --disable-werror + echo -e "\\nRISC-V OpenOCD installation completed!" + cd $RDIR + fi +fi diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index 53dee5a..302294b 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -7,12 +7,12 @@ set -o pipefail RDIR=$(pwd) scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" -sims_dir=$scripts_dir/../sims/ + +cd $scripts_dir/.. # Reenable the FireSim submodule git config --unset submodule.sims/firesim.update || true -cd $sims_dir -git submodule update --init firesim -cd firesim +git submodule update --init sims/firesim +cd sims/firesim ./build-setup.sh $@ --library cd $RDIR diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 8bf6b30..3a95f5c 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -11,16 +11,19 @@ scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" # ignore riscv-tools for submodule init recursive # you must do this globally (otherwise riscv-tools deep # in the submodule tree will get pulled anyway -git config --global submodule.riscv-tools.update none -git config --global submodule.esp-tools.update none +git config submodule.toolchains/riscv-tools.update none +git config submodule.toolchains/esp-tools.update none git config --global submodule.experimental-blocks.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none +# Disable updates to the hammer-cad-plugins repo +git config submodule.vlsi/hammer-cad-plugins.update none git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally -git config --global --unset submodule.riscv-tools.update -git config --global --unset submodule.esp-tools.update +git config --unset submodule.toolchains/riscv-tools.update +git config --unset submodule.toolchains/esp-tools.update git config --global --unset submodule.experimental-blocks.update +git config --unset submodule.vlsi/hammer-cad-plugins.update # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh new file mode 100755 index 0000000..294f862 --- /dev/null +++ b/scripts/init-vlsi.sh @@ -0,0 +1,13 @@ +#!/usr/bin/env bash +# exit script if any command fails +set -e +set -o pipefail + + + +# Initialize HAMMER and CAD-plugins +git submodule update --init --recursive vlsi/hammer +git submodule update --init --recursive vlsi/hammer-cad-plugins + +# Initialize HAMMER tech plugin +git submodule update --init --recursive vlsi/hammer-$1-plugin \ No newline at end of file diff --git a/sims/firesim b/sims/firesim index 7f8152e..4cd7583 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7f8152e5114c7f7793df54a41a53a9e6a04fa8cd +Subproject commit 4cd75833dfc1f9f796a1c5505ece6937fd253189 diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index c97f984..d717aa6 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -40,6 +40,31 @@ debug: $(sim_debug) include $(base_dir)/common.mk include $(sim_dir)/verilator.mk +######################################################################################### +# verilator binary and flags +######################################################################################### +VERILATOR := $(INSTALLED_VERILATOR) --cc --exe + +CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS +LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread + +VERILATOR_CC_OPTS = \ + -O3 \ + -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \ + -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs" \ + -LDFLAGS "$(LDFLAGS)" + +VERILATOR_NONCC_OPTS = \ + --top-module $(VLOG_MODEL) \ + +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ + +define+STOP_COND=\$$c\(\"done_reset\"\) \ + --assert \ + --output-split 20000 \ + $(sim_vsrcs) \ + -f $(sim_common_files) + +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) + ######################################################################################### # verilator build paths and file names ######################################################################################### @@ -55,41 +80,27 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules ######################################################################################### -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread -SHARED_FLAGS := \ - $(sim_vsrcs) \ - -f $(sim_common_files) \ - -LDFLAGS "$(LDFLAGS)" $(model_mk): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) - $(VERILATOR) $(VERILATOR_FLAGS) \ - -Mdir $(build_dir)/$(long_name) \ - -o $(sim) \ - $(SHARED_FLAGS) \ - -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)" + $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug - $(VERILATOR) $(VERILATOR_FLAGS) \ - -Mdir $(build_dir)/$(long_name).debug \ - --trace \ - -o $(sim_debug) \ - $(SHARED_FLAGS) \ - -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)" + $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ ######################################################################################### # invoke make to make verilator sim rules ######################################################################################### $(sim): $(model_mk) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk $(sim_debug): $(model_mk_debug) - $(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk + $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk ######################################################################################### # create a verilator vpd rule diff --git a/sims/verilator/verilator.mk b/sims/verilator/verilator.mk index 0ea53a1..12ab165 100644 --- a/sims/verilator/verilator.mk +++ b/sims/verilator/verilator.mk @@ -37,16 +37,3 @@ $(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VE $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz: mkdir -p $(dir $@) wget https://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ - -######################################################################################### -# verilator binary and flags -######################################################################################### -VERILATOR := $(INSTALLED_VERILATOR) --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) \ - --assert \ - --output-split 20000 \ - -Wno-STMTDLY --x-assign unique \ - -O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" diff --git a/vlsi/.gitignore b/vlsi/.gitignore new file mode 100644 index 0000000..4cbcfe8 --- /dev/null +++ b/vlsi/.gitignore @@ -0,0 +1,6 @@ +inputs.yml +__pycache__ +hammer*.log +build +src/test/output-*.json +generated-src \ No newline at end of file diff --git a/vlsi/Makefile b/vlsi/Makefile new file mode 100644 index 0000000..fc0b4ac --- /dev/null +++ b/vlsi/Makefile @@ -0,0 +1,122 @@ +######################################################################################### +# vlsi makefile +######################################################################################### + +######################################################################################### +# general path variables +######################################################################################### +base_dir=$(abspath ..) +vlsi_dir=$(abspath .) +sim_dir=$(abspath .) + +######################################################################################### +# include shared variables +######################################################################################### +include $(base_dir)/variables.mk + +######################################################################################### +# import other necessary rules and variables +######################################################################################### +include $(base_dir)/common.mk + +######################################################################################### +# vlsi types and rules +######################################################################################### + +#sim_name is unused, but GenerateSimFiles expects it +sim_name ?= vcs +tech_name ?= +tech_dir ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name) +SMEMS_COMP ?= $(tech_dir)/sram-compiler.json +SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json +MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) +OBJ_DIR ?= $(vlsi_dir)/build +ENV_YML ?= $(vlsi_dir)/bwrc-env.yml +INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml +HAMMER_EXEC ?= ./example-vlsi + +ROCKET_SRC_DIR=$(ROCKETCHIP_DIR)/src/main/resources/vsrc + +ROCKET_SRCS = \ + $(ROCKET_SRC_DIR)/ClockDivider2.v \ + $(ROCKET_SRC_DIR)/ClockDivider3.v \ + $(ROCKET_SRC_DIR)/AsyncResetReg.v \ + $(ROCKET_SRC_DIR)/plusarg_reader.v \ + $(ROCKET_SRC_DIR)/EICG_wrapper.v \ + +ALL_RTL = $(ROCKET_SRCS) $(TOP_FILE) $(TOP_SMEMS_FILE) + +CLOCK_DOMAINS = $(build_dir)/$(long_name).domains + +.PHONY: default +default: all + +all: drc lvs + + +###################################################### SYN ############################################################ + +SYNTH_CONF = $(OBJ_DIR)/inputs.yml + +$(SYNTH_CONF): + mkdir -p $(dir $@) + echo "synthesis.inputs:" > $@ + echo " top_module: $(TOP)" >> $@ + echo " input_files:" >> $@ + for x in $(ALL_RTL); do \ + echo ' - "'$$x'"' >> $@; \ + done + +GENERATED_CONFS=$(SYNTH_CONF) $(SRAM_CONF) + +.PHONY: syn synthesis +syn: $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v +synthesis: syn + +$(OBJ_DIR)/syn-rundir/$(TOP).mapped.v $(OBJ_DIR)/syn-rundir/syn-output.json: $(ENV_YML) $(INPUT_CONFS) $(GENERATED_CONFS) $(ALL_RTL) + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) syn + +$(OBJ_DIR)/par-input.json: $(OBJ_DIR)/syn-rundir/syn-output.json + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $<, -p $(x)) -o $@ syn_to_par + +###################################################### PAR ############################################################ + +.PHONY: par place-and-route +par: $(OBJ_DIR)/par-rundir/$(TOP).gds +place-and-route: par + +$(OBJ_DIR)/par-rundir/$(TOP).gds $(OBJ_DIR)/par-rundir/par-output.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/syn-rundir/$(TOP).mapped.v + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) par + +$(OBJ_DIR)/drc-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_drc + +###################################################### DRC ############################################################ +# TODO unimplemented +.PHONY: drc +drc: $(OBJ_DIR)/drc-rundir/drc_results.db + +$(OBJ_DIR)/drc-rundir/drc_results.db: $(OBJ_DIR)/drc-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) drc + +###################################################### LVS ############################################################ +# TODO unimplemented +$(OBJ_DIR)/lvs-input.json: $(OBJ_DIR)/par-input.json $(OBJ_DIR)/par-rundir/par-output.json + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$^, -p $(x)) -o $@ --obj_dir $(OBJ_DIR) par_to_lvs + +.PHONY: lvs +lvs: $(OBJ_DIR)/lvs-rundir/lvs_results.rpt + +$(OBJ_DIR)/lvs-rundir/lvs_results.rpt: $(OBJ_DIR)/lvs-input.json $(OBJ_DIR)/par-rundir/$(TOP).gds + mkdir -p $(dir $@) + $(HAMMER_EXEC) -e $(ENV_YML) -p $< --obj_dir $(OBJ_DIR) lvs + +.PHONY: clean +clean: + rm -rf $(OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) generated-src diff --git a/vlsi/README.md b/vlsi/README.md new file mode 100644 index 0000000..aa07dd0 --- /dev/null +++ b/vlsi/README.md @@ -0,0 +1,9 @@ +This is the starting point for a vlsi flow from this repository. + +This flow will not work without the necessary CAD and technology plugins for HAMMER. + +If you are a UCB-affiliate, you may be able to acquire access to the tech-plugins. + +# Initial Setup Instructions (For All technologies) +Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-cad-plugins, and the hammer-tech-plugins +```scripts/init-vlsi.sh TECH_NAME``` \ No newline at end of file diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi new file mode 100755 index 0000000..3f65d9a --- /dev/null +++ b/vlsi/example-vlsi @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 + +import hammer_vlsi +from hammer_vlsi import CLIDriver, HammerToolHookAction + +from typing import Dict, Callable, Optional, List + +def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: + x.append(''' +# TODO +''') + return True + +class ExampleDriver(CLIDriver): + def get_extra_par_hooks(self) -> List[HammerToolHookAction]: + return [hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells)] + +if __name__ == '__main__': + ExampleDriver().main() diff --git a/vlsi/hammer b/vlsi/hammer new file mode 160000 index 0000000..873b2c1 --- /dev/null +++ b/vlsi/hammer @@ -0,0 +1 @@ +Subproject commit 873b2c1af0a54cb339a19a7c8cf3a1e7905feb58 diff --git a/vlsi/hammer-cad-plugins b/vlsi/hammer-cad-plugins new file mode 160000 index 0000000..72809f5 --- /dev/null +++ b/vlsi/hammer-cad-plugins @@ -0,0 +1 @@ +Subproject commit 72809f538c4bbe91c103de52e92baad9df6d8f9a