725 lines
23 KiB
Perl
725 lines
23 KiB
Perl
#!/usr/bin/perl
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use warnings;
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use strict;
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use Cwd;
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use File::Copy;
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use List::Util qw(first);
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my $dir = getcwd;
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my $file_name = $ARGV[0];
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my $func_name = $ARGV[1];
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my $rdir = $ENV{'RDIR'};
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my $prefix = undef;
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my $num_args = $#ARGV + 1;
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if ($num_args > 2) {
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$prefix = $ARGV[2];
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}
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if ($prefix) {
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$func_name = $prefix.$func_name;
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}
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#print $rdir;
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if ((not defined($rdir)) or $rdir eq '') {
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print("Please source sourceme-f1.sh!\n");
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exit();
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}
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my $verilog_file = "$dir/../verilog/$func_name".".v";
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my $line = undef;
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my @verilog_input = ();
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my @verilog_input_size = ();
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my @verilog_output = ();
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my @verilog_output_size = ();
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print "Parsing ".$verilog_file."\n";
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# parse the verilog file to get the info we need
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if(!open VERILOG, "$verilog_file"){
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print $!;
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} else {
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while(<VERILOG>){
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$line = $_;
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if($line =~ m/^\s*input\s+(.*)/){
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my $input = $1;
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#print "input:$input\n";
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if($input =~ m/\s*\[(.*):(.*)\]\s*(.*)\s*;/){
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my $end = $1;
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my $start = $2;
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my $input_name = $3;
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#print "here!"."$input_name\n";
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push (@verilog_input, $input_name);
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my $size = $end - $start + 1;
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push(@verilog_input_size, $size);
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}elsif ($input =~ m/\s*(.*)\s*;/){
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my $input_name = $1;
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#print "here!"."$input_name\n";
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push (@verilog_input, $input_name);
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push(@verilog_input_size, 1);
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}
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}elsif($line =~ m/^\s*output\s+(.*)/){
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my $output = $1;
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#print "output:$output\n";
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if($output =~ m/\s*\[(.*):(.*)\]\s*(.*)\s*;/){
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my $end = $1;
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my $start = $2;
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my $output_name = $3;
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#print "here!"."$output_name\n";
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push(@verilog_output, $output_name);
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my $size = $end - $start + 1;
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push(@verilog_output_size, $size);
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}elsif ($output =~ m/\s*(.*)\s*;/){
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my $output_name = $1;
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#print "here!"."$output_name\n";
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push (@verilog_output, $output_name);
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push(@verilog_output_size, 1);
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}
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}
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}
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print("Inputs:");
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my $in_str = join ' ', @verilog_input;
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print $in_str."\n";
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print("Outputs:");
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my $out_str = join ' ', @verilog_output;
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print $out_str."\n";
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}
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#creat scala folder
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my $scala_dir = "$dir/../scala";
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mkdir $scala_dir unless (-d $scala_dir);
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##############################################################################################################################
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print "Generating BlackBox file ...\n";
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# should be under scala folder
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open BB, ">$scala_dir/$func_name"."_blackbox.scala";
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my $blackbox1 = "
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package hls_test_c
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import Chisel._
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import chisel3.experimental.dontTouch
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.util._
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import vivadoHLS._
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class test_c() extends BlackBox() {
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";
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$blackbox1 =~ s/test_c/$func_name/g;
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print BB $blackbox1;
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print BB "\tval io = new Bundle {\n";
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my $i = undef;
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my $bb_body = "";
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# now if the input name does not start with ap, we assume it is an arg
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my $ap_return = 0;
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my $ap_clk = 0;
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my $ap_rst = 0;
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my @verilog_input_scalar = ();
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my %verilog_input_pointer = ();
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my @verilog_input_pointer_arg = (); # An ordered list of args
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my $arg_count = 0;
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my @sindices = ();
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my @pindices = ();
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for( $i = 0; $i < @verilog_input; $i = $i + 1 ){
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my $input_name = $verilog_input[$i];
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my $input_size = $verilog_input_size[$i];
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if ($input_name =~ m/ap_clk(.*)/){
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$ap_clk = 1;
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}
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elsif ($input_name =~ m/ap_rst(.*)/){
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$ap_rst = 1;
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}
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# If the input is a ap_bus port, the signals should match the following format
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# There should be 3 different input signals
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elsif($input_name =~ m/(\S+)_req_full_n/ or $input_name =~ m/(\S+)_rsp_empty_n/ or $input_name =~ m/(\S+)_datain/){
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my $arg_name = $1;
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if ($input_name =~ m/(\S+)_datain/) {
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push(@pindices, $arg_count);
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$arg_count = $arg_count + 1;
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push(@verilog_input_pointer_arg, $arg_name);
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}
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if (defined $verilog_input_pointer{$arg_name}) {
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$verilog_input_pointer{$arg_name} += 1;
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} else {
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$verilog_input_pointer{$arg_name} = 1;
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}
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}
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elsif(!($input_name =~ m/ap_(,*)/)){
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push (@verilog_input_scalar, $input_name);
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push(@sindices, $arg_count);
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$arg_count = $arg_count + 1;
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}
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else{
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print("Not func args: $input_name\n");
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}
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print BB "\t\tval $input_name = ";
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if ($input_name =~ m/ap_clk(.*)/){
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print BB "Clock\(INPUT\)\n";
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}else{
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if ($input_size == 1){
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print BB "Bool\(INPUT\)\n";
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}else{
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print BB "Bits\(INPUT, width = $input_size\)\n";
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}
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}
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if($input_name ne "ap_clk" && $input_name ne "ap_rst"){
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$bb_body = $bb_body."\tio.".$input_name.".setName(\"".$input_name."\")\n";
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}
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}
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#foreach my $arg (keys %verilog_input_pointer) {
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foreach my $arg (@verilog_input_pointer_arg) {
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print("pointer_arg: $arg\n");
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}
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my $hash_count = keys %verilog_input_pointer;
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print("hash_count: $hash_count\n");
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if(@verilog_input_scalar + $hash_count> 2){
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print "verilog_input_scalar: ";
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my $in_str = join ' ', @verilog_input_scalar;
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print $in_str."\n";
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die "Only accept function with no more than 2 arguments!\n";
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}
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foreach my $arg (keys %verilog_input_pointer) {
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if ($verilog_input_pointer{$arg} ne 3) {
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die "The AP bus interfance did not generate expected number of inputs!\n";
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}
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}
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for( $i = 0; $i < @verilog_output; $i = $i + 1 ){
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my $output_name = $verilog_output[$i];
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my $output_size = $verilog_output_size[$i];
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if ($output_name =~ m/ap_return(.*)/){
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$ap_return = 1;
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}
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print BB "\t\tval $output_name = ";
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if ($output_size == 1){
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print BB "Bool(OUTPUT)\n";
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}else{
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print BB "Bits(OUTPUT, width = $output_size)\n";
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}
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$bb_body = $bb_body."\tio.".$output_name.".setName(\"".$output_name."\")\n";
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}
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if ($ap_clk eq 1){
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$bb_body = $bb_body."addClock(Driver\.implicitClock)\n".'renameClock("clk", "ap_clk")'."\n";
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}
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if ($ap_rst eq 1){
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$bb_body = $bb_body.'renameReset("ap_rst")'."\n";
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}
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print BB "\t}\n";
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#print BB "$bb_body\n";
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#print BB "moduleName = "."\"$func_name\"\n";
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print BB "}\n";
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my $bb_def = "class HLS$func_name"."Blackbox() extends Module {\n";
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# Scalar IO Parameter
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my @sdata_widths = ();
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#my @sindices = ();
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#my $sidx = 0;
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foreach my $arg (@verilog_input_scalar) {
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my $sdata_idx = first { $verilog_input[$_] eq $arg} 0..$#verilog_input;
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my $sdata_width = $verilog_input_size[$sdata_idx];
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push(@sdata_widths, $sdata_width);
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#push(@sindices, $sidx);
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#$sidx += 1;
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}
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my $sindices_str = join ',',@sindices;
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my $sdata_widths_str = join ',',@sdata_widths;
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print "scalar data_widths: $sdata_widths_str\n";
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$bb_def .= "\tval scalar_io_dataWidths = List($sdata_widths_str)\n";
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$bb_def .= "\tval scalar_io_argLoc = List($sindices_str) //Lists the argument number of the scalar_io\n";
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# Pointer IO Parameter
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my @addr_widths = ();
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my @data_widths = ();
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#my @indices = ();
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my $idx = 0;
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foreach my $arg (sort keys %verilog_input_pointer) {
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my $addr_signal = $arg."_address";
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my $data_signal = $arg."_dataout";
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my $addr_idx = first { $verilog_output[$_] eq $addr_signal } 0..$#verilog_output;
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my $data_idx = first { $verilog_output[$_] eq $data_signal } 0..$#verilog_output;
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#my $addr_width = $verilog_output_size[$addr_idx];
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my $addr_width = "64";
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my $data_width = $verilog_output_size[$data_idx];
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push(@addr_widths, $addr_width);
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push(@data_widths, $data_width);
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#push(@indices, $idx);
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$idx += 1;
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}
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#my $indices_str = join ',',@indices;
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my $pindices_str = join ',',@pindices;
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my $addr_widths_str = join ',',@addr_widths;
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print "addr_widths: $addr_widths_str\n";
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my $data_widths_str = join ',',@data_widths;
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print "data_widths: $data_widths_str\n";
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$bb_def .= "\tval ap_bus_addrWidths = List(".$addr_widths_str.")\n";
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$bb_def .= "\tval ap_bus_dataWidths = List(".$data_widths_str.")\n";
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#$bb_def .= "\tval ap_bus_argLoc = List(".$indices_str.")\n";
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$bb_def .= "\tval ap_bus_argLoc = List(".$pindices_str.")\n";
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my $ret_width = 1;
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if ($ap_return eq 1){
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my $ret_idx = first { $verilog_output[$_] eq 'ap_return'} 0..$#verilog_output;
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$ret_width = $verilog_output_size[$ret_idx];
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}
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$bb_def .= "\tval io = new Bundle {
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\tval ap = new ApCtrlIO(dataWidth = $ret_width)
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\tval ap_bus = HeterogeneousBag(ap_bus_addrWidths.zip(ap_bus_dataWidths).map {
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case (aw, dw) => new ApBusIO(dw, aw)
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})
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";
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if (@verilog_input_scalar > 0){
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$bb_def .="\tval scalar_io = HeterogeneousBag(scalar_io_dataWidths.map(w => UInt(INPUT, width = w)))";
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}
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$bb_def .="
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}
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\tval bb = Module(new $func_name())
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\tbb.io.ap_start := io.ap.start
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\tio.ap.done := bb.io.ap_done
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\tio.ap.idle := bb.io.ap_idle
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\tio.ap.ready := bb.io.ap_ready
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";
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if ($ap_return eq 1) {
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$bb_def .= "\tio.ap.rtn := bb.io.ap_return\n";
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}
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if ($ap_rst eq 1) {
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$bb_def .= "\tbb.io.ap_rst := reset\n";
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}
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if ($ap_clk eq 1) {
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$bb_def .= "\tbb.io.ap_clk := clock\n";
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}
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$idx = 0;
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#foreach my $arg (keys %verilog_input_pointer) {
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foreach my $arg (@verilog_input_pointer_arg) {
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$bb_def.="\tio.ap_bus($idx).req.din := bb.io.$arg"."_req_din
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\tbb.io.$arg"."_req_full_n := io.ap_bus($idx).req_full_n
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\tio.ap_bus($idx).req_write := bb.io.$arg"."_req_write
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\tbb.io.$arg"."_rsp_empty_n := io.ap_bus($idx).rsp_empty_n
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\tio.ap_bus($idx).rsp_read := bb.io.$arg"."_rsp_read
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\tio.ap_bus($idx).req.address := bb.io.$arg"."_address
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\tbb.io.$arg"."_datain := io.ap_bus($idx).rsp.datain
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\tio.ap_bus($idx).req.dataout := bb.io.$arg"."_dataout
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\tio.ap_bus($idx).req.size := bb.io.$arg"."_size
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";
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$idx += 1;
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}
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$idx = 0;
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foreach my $arg (@verilog_input_scalar) {
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$bb_def .="\tbb.io.$arg := io.scalar_io($idx)\n";
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$idx += 1;
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}
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$bb_def .= "}";
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print BB $bb_def;
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close BB;
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##############################################################################################################################
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print "Copying Vivado HLS Interface file ...\n";
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copy("$rdir/tools/centrifuge/scripts/chisel_rocc_aux/ap_bus.scala", "$scala_dir/") or die "Copy failed: $!";
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##############################################################################################################################
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print "Copying ROCC Memory Controller file ...\n";
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copy("$rdir/tools/centrifuge/scripts/chisel_rocc_aux/memControllerComponents.scala", "$scala_dir/") or die "Copy failed: $!";
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##############################################################################################################################
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print "Copying Controller Utilities file ...\n";
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copy("$rdir/tools/centrifuge/scripts/chisel_rocc_aux/controlUtils.scala", "$scala_dir/") or die "Copy failed: $!";
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##############################################################################################################################
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print "Generating Control file ...\n";
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open CT, ">$scala_dir/$func_name"."_accel.scala";
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my $control1 = '
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package hls_test_c
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import Chisel._
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import chisel3.experimental.dontTouch
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import freechips.rocketchip.system._
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import vivadoHLS._
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import memControl._
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import hls_test_c._
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class HLStest_cControl(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes) {
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override lazy val module = new HLStest_cControlModule(this)
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}
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class HLStest_cControlModule(outer: HLStest_cControl)(implicit p: Parameters) extends LazyRoCCModuleImp(outer)
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with HasCoreParameters {
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';
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$control1 =~ s/test_c/$func_name/g;
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print CT $control1;
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#TODO modify accelerator arg!
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my $control2 = '
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val result = Reg(init=Bits(0, width=xLen))
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val respValid = Reg(init=Bool(false))
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val rdy = Reg(init=Bool(true))
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val busy = Reg(init=Bool(false))
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val bufferedCmd = Reg(init=Wire( new RoCCCommand()(p)))
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val cmd = Queue(io.cmd)
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val funct = bufferedCmd.inst.funct
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val rs1 = bufferedCmd.rs1
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val rs2 = bufferedCmd.rs2
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val rdTag = bufferedCmd.inst.rd
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val doAdd = funct === UInt(0)
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val rs1_unbuffered = cmd.bits.rs1
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val rs2_unbuffered = cmd.bits.rs2
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val idle :: working :: Nil = Enum(UInt(),2)
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val state = Reg(init=idle)
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when(reset.toBool){
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bufferedCmd.inst.funct := 0.asUInt(7.W)
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bufferedCmd.inst.rs1 := 0.asUInt(5.W)
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bufferedCmd.inst.rs2 := 0.asUInt(5.W)
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bufferedCmd.inst.rd := 0.asUInt(5.W)
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bufferedCmd.inst.opcode := 0.asUInt(5.W)
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bufferedCmd.rs1 := 0.asUInt(64.W)
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bufferedCmd.rs2 := 0.asUInt(64.W)
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}
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// Assign Outputs to Appropriate registers
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io.resp.valid := respValid && bufferedCmd.inst.xd
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//need to set rd to the value in the request. Otherwise bad things happen
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//in this case, processor stalls
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io.resp.bits.rd := rdTag
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io.resp.bits.data := result
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io.busy := busy
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cmd.ready := rdy
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//===== Begin Accelerator =====
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val accel = Module(new HLStest_cBlackbox())
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//Acclerator Registers (we buffer inputs to accelerator)
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val ap_start = Reg(init=Bool(false))
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//Assign Inputs to Accelerator
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accel.io.ap.start := ap_start
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';
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#accel.io.test_c_rs1 := rs1 //ACCEL IO NAME CAN CHANGE (NAMED IN C)
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#accel.io.test_c_rs2 := rs2 //ACCEL IO NAME CAN CHANGE (NAMED IN C)
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#my $rs1 = $verilog_input_scalar[0];
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#my $rs2 = $verilog_input_scalar[1];
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for( $i = 0; $i < @verilog_input_scalar; $i = $i + 1 ){
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my $number = $i + 1;
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$control2 = $control2."accel.io.scalar_io($i) := rs$number\n";
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}
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if ($ap_return eq 1){
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$control2 = $control2."val ap_return = accel.io.ap.rtn\n";
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}else{
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$control2 = $control2."val ap_return = UInt(4)\n";
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}
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$control2 = $control2.'//Accelerator Outputs
|
|
val ap_done = accel.io.ap.done
|
|
val ap_idle = accel.io.ap.idle
|
|
val ap_ready = accel.io.ap.ready
|
|
|
|
//===== End Accelerator =====
|
|
|
|
//===== Begin Mem Controller =====
|
|
//The following are specific to the accelerator. They set the address and data widths of the ap_bus interfaces
|
|
val dataWidth = accel.ap_bus_dataWidths
|
|
val addrWidth = accel.ap_bus_addrWidths
|
|
val reqBufferLen = 4
|
|
val rspBufferLen = 4
|
|
val maxReqBytes = xLen/8
|
|
val roccAddrWidth = coreMaxAddrBits
|
|
val roccDataWidth = coreDataBits
|
|
val roccTagWidth = coreDCacheReqTagBits
|
|
val roccCmdWidth = M_SZ
|
|
val roccTypWidth = log2Ceil(coreDataBytes.log2 + 1)
|
|
//val numTags = p(RoccMaxTaggedMemXacts)
|
|
val numTags = 16
|
|
val tagOffset = 0 //Used if multiple accelerators to avoid tag collisions
|
|
|
|
//Instantiate Controller
|
|
val memControl = Module(new MemController(dataWidth, addrWidth, reqBufferLen, rspBufferLen, maxReqBytes, roccAddrWidth, roccDataWidth, roccTagWidth, roccCmdWidth, roccTypWidth, numTags, tagOffset))
|
|
|
|
if(accel.io.ap_bus.length > 0){
|
|
//We have memory bus interfaces on the accelerator, create a memory controller
|
|
|
|
//Hook up controller
|
|
for(i <- 0 until accel.io.ap_bus.length){
|
|
//memControl.io.reqsIn(i) <> accel.io.ap_bus(i).req
|
|
memControl.io.reqsIn(i) := accel.io.ap_bus(i).req
|
|
|
|
accel.io.ap_bus(i).req_full_n := memControl.io.reqsFullN(i)
|
|
|
|
memControl.io.reqsWrite(i) := accel.io.ap_bus(i).req_write
|
|
|
|
accel.io.ap_bus(i).rsp.datain := memControl.io.rspOut(i).datain
|
|
accel.io.ap_bus(i).rsp_empty_n := memControl.io.rsp_empty_n(i)
|
|
memControl.io.rsp_read(i) := accel.io.ap_bus(i).rsp_read
|
|
}
|
|
io.mem.req.bits.addr := memControl.io.roCCReqAddr
|
|
io.mem.req.bits.tag := memControl.io.roCCReqTag
|
|
io.mem.req.bits.cmd := memControl.io.roCCReqCmd
|
|
io.mem.req.bits.size := memControl.io.roCCReqTyp
|
|
|
|
// If the address is not a mulitple of 8 byte which the coreDataBits width,
|
|
// We have to shift the N-bit data to the right place in a 64-bit word
|
|
val shift = (memControl.io.roCCReqAddr & UInt( log2Up(coreDataBits) - 1 )) << UInt(3)
|
|
io.mem.req.bits.data := memControl.io.roCCReqData << shift(7,0)
|
|
io.mem.req.valid := memControl.io.roCCReqValid
|
|
memControl.io.roCCReqRdy := io.mem.req.ready
|
|
//io.mem.req.bits.phys := Bool(true)
|
|
|
|
//val roCCRespAddr = UInt(INPUT, width = roccAddrWidth) // coreMaxAddrBits)
|
|
memControl.io.roCCRspTag := io.mem.resp.bits.tag
|
|
memControl.io.roCCRspCmd := io.mem.resp.bits.cmd
|
|
memControl.io.roCCRspData := io.mem.resp.bits.data
|
|
//val roCCRespTyp
|
|
memControl.io.roCCRspValid := io.mem.resp.valid
|
|
}
|
|
|
|
//===== End Mem Controller =====
|
|
';
|
|
# The sequence of arg 1 and 2 depends on the sequence they show up in the verilog file
|
|
# TODO think about a better way to add this
|
|
|
|
$control2 .= '//===== Begin Argument Handling =====
|
|
//TODO: currently only works for 2 argument calls. Generalize
|
|
|
|
val cArgs = List(rs1, rs2)
|
|
val cArgsUnbuffered = List(rs1_unbuffered, rs2_unbuffered)
|
|
//Argument numbers are specified in the blackbox
|
|
';
|
|
|
|
if (@verilog_input_scalar > 0){
|
|
$control2 .= '//Scalar values
|
|
for(i <- 0 until accel.io.scalar_io.length){
|
|
accel.io.scalar_io(i) := cArgs(accel.scalar_io_argLoc(i))
|
|
}
|
|
';
|
|
}
|
|
|
|
$control2 .= '//ap_bus offsets
|
|
for(i <- 0 until memControl.io.offsetAddrs.length){
|
|
//ap_bus uses the unbuffered input because it is buffered on the first cycle
|
|
memControl.io.offsetAddrs(i) := cArgsUnbuffered(accel.ap_bus_argLoc(i))
|
|
}
|
|
//===== End Argument Handling =====
|
|
';
|
|
|
|
|
|
$control2 .='
|
|
if(accel.io.ap_bus.length > 0){
|
|
//Will run ap_start after offsets loaded
|
|
for(i <- 0 until memControl.io.loadOffsets.length){
|
|
memControl.io.loadOffsets(i) := (state === idle) && cmd.fire()
|
|
}
|
|
}
|
|
|
|
|
|
//===== Begin Controller State Machine Logic =====
|
|
switch(state){
|
|
is (idle){
|
|
//Waiting for command
|
|
|
|
when(cmd.fire()){
|
|
//We have a valid, unserviced command. This code takes ready low so
|
|
//we should not accedently cause an infinite loop
|
|
|
|
bufferedCmd := cmd.bits //Accelerator takes from bufferedCmd directly
|
|
busy := Bool(true)
|
|
rdy := Bool(false)
|
|
|
|
//Load the offsets
|
|
/*if(accel.io.ap_bus.length > 0){
|
|
//Will run ap_start after offsets loaded
|
|
for(i <- 0 until memControl.io.loadOffsets.length){
|
|
memControl.io.loadOffsets(i) := Bool(true)
|
|
}
|
|
}*/
|
|
|
|
ap_start := Bool(true) //Set next state
|
|
state := working
|
|
//Note: Based on timing diagram in Vivado HLS user guide (pg 157), read occurs
|
|
//AFTER the 1st cycle. There will be a 1 cycle delay before input read as
|
|
//ap_start will be seen on next cycle. Idealy, ap_start would be raised 1 cycle
|
|
//earlier (ie. not using a register) or it would read the input immediatly
|
|
//when ap_start is raised (I assume this is due to an internal state machine).
|
|
//However, this would ruin the sequential nature of the state machine. It is
|
|
//possible to save a cycle by assigning ap_start as cmd.valid && state===idle
|
|
//&& !returned which would be asyncronous and probably trigger 1 cycle earlier.
|
|
//There would be more stringent timing requirements in this case though as the
|
|
//result would need to propogate before the next posEdge of the clk.
|
|
|
|
|
|
}
|
|
when(respValid && io.resp.ready){
|
|
//The processor has read the response. There is no more data for it
|
|
//Drive resp.valid low to avoid stalling processor
|
|
respValid := Bool(false)
|
|
}
|
|
}
|
|
is (working){
|
|
|
|
//Stop Loading offsets
|
|
/*if(accel.io.ap_bus.length > 0){
|
|
//Will run ap_start after offsets loaded
|
|
for(i <- 0 until memControl.io.loadOffsets.length){
|
|
memControl.io.loadOffsets(i) := Bool(false)
|
|
}
|
|
}*/
|
|
|
|
//Waiting for accelerator to finish
|
|
|
|
//All of the conditionals below can occure simultaniously
|
|
//and should be kept as seperart when statements
|
|
when(ap_done){
|
|
//The accelerator has completed operation (user guidepg 156) and has
|
|
//has optionally generated a result (not not all accelerators will
|
|
//generated a result. This is technically not the same as ap_idle
|
|
//which signals when the accelerator is no longer busy. It is actually
|
|
//ap_ready actually determines when the accelerator is ready to accept
|
|
//more inputs. This is important for accelerators that do not operate
|
|
//in a syncronous mode. This is not true for the types of accelerators
|
|
//we are creating.
|
|
|
|
result := ap_return
|
|
respValid := Bool(true)
|
|
}
|
|
when(ap_ready){
|
|
//The accelerator has read the inputs and is ready to accept new ones.
|
|
//According to the timing diagram,
|
|
//ap_start should be deasserted for the next posedge.
|
|
ap_start := Bool(false)
|
|
}
|
|
|
|
|
|
if(accel.io.ap_bus.length == 0){
|
|
when(ap_idle){
|
|
//if the operation was completed (result valid), and the accelerator is ready
|
|
//the accerator is ready for the next operation and the controller is
|
|
//returned to the idle state to wait for a new command. the ready line
|
|
//is pulled high to advertise that the accelerator is ready.
|
|
|
|
//from the manual, it appears that ap_done is always asserted when the
|
|
//accelerator is finished. if this is true, using ap_done && ap_ready
|
|
//should save one cycle over using ap_idle as the trigger. this is because,
|
|
//according to the timing diagram in the user manual (pg
|
|
|
|
rdy := Bool(true) // ready to accept new commands
|
|
busy := Bool(false) // operation complete, no longer busy
|
|
state := idle
|
|
|
|
//note: this code could possibly be placed in the ap_done action to save
|
|
//one wasted cycle. it is not clear from the user guide (pg 157), ap_idle
|
|
//is asserted one cycle after ap_done. if this arrangment has problems,
|
|
//transitioning on ap_idle should work but will result in an unnessicary
|
|
//extra cycle.
|
|
}
|
|
}
|
|
else
|
|
{
|
|
when(ap_idle && !memControl.io.memBusy){
|
|
//if the operation was completed (result valid), and the accelerator is ready
|
|
//the accerator is ready for the next operation and the controller is
|
|
//returned to the idle state to wait for a new command. the ready line
|
|
//is pulled high to advertise that the accelerator is ready.
|
|
|
|
//from the manual, it appears that ap_done is always asserted when the
|
|
//accelerator is finished. if this is true, using ap_done && ap_ready
|
|
//should save one cycle over using ap_idle as the trigger. this is because,
|
|
//according to the timing diagram in the user manual (pg
|
|
|
|
rdy := Bool(true) // ready to accept new commands
|
|
busy := Bool(false) // operation complete, no longer busy
|
|
state := idle
|
|
|
|
//note: this code could possibly be placed in the ap_done action to save
|
|
//one wasted cycle. it is not clear from the user guide (pg 157), ap_idle
|
|
//is asserted one cycle after ap_done. if this arrangment has problems,
|
|
//transitioning on ap_idle should work but will result in an unnessicary
|
|
//extra cycle.
|
|
}
|
|
}
|
|
when(respValid && io.resp.ready){
|
|
//The processor has read the response. There is no more data for it
|
|
//Drive resp.valid low to avoid stalling processor
|
|
respValid := Bool(false)
|
|
}
|
|
}
|
|
}
|
|
|
|
// ===== End Controller State Machine Logic =====
|
|
|
|
// ===== Tie off these lines =====
|
|
io.interrupt := Bool(false)
|
|
// Set this true to trigger an interrupt on the processor (please refer to supervisor documentation)
|
|
|
|
// MEMORY REQUEST INTERFACE
|
|
if(accel.io.ap_bus.length == 0){
|
|
// No connected memory bus lines on accelerator
|
|
// We will not be doing any memory ops in this accelerator
|
|
io.mem.req.valid := Bool(false)
|
|
io.mem.req.bits.addr := UInt(0)
|
|
io.mem.req.bits.tag := UInt(0)
|
|
io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
|
|
io.mem.req.bits.size := log2Ceil(8).U
|
|
io.mem.req.bits.signed := Bool(false)
|
|
io.mem.req.bits.data := UInt(0) // not performing any stores
|
|
}
|
|
//io.mem.invalidate_lr := Bool(false)
|
|
|
|
//If enable physical addr, make sure to use pmp instr to set the right permission on addr range
|
|
io.mem.req.bits.phys := Bool(false)
|
|
';
|
|
|
|
|
|
$control2 .= "}\n";
|
|
# TODO no clock and reset signal
|
|
$control2 =~ s/test_c/$func_name/g;
|
|
|
|
print CT $control2;
|
|
|
|
|