561 lines
17 KiB
Perl
561 lines
17 KiB
Perl
#!/usr/bin/perl
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use warnings;
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use strict;
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use Cwd;
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use File::Copy;
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use List::Util qw(first);
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# Inputs: file_name, func_name, func_base_addr, prefix(Optional)
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my $dir = getcwd;
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my $file_name = $ARGV[0];
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my $func_name = $ARGV[1];
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my $func_base_addr = $ARGV[2];
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my $rdir = $ENV{'RDIR'};
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my $prefix = undef;
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my $i = undef;
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my $num_args = $#ARGV + 1;
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if ($num_args > 3) {
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$prefix = $ARGV[3];
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}
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#my $bm_path = $rdir."/sim/target-rtl/firechip/hls_$file_name"."_$func_name";
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if ($prefix) {
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$func_name = $prefix.$func_name;
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}
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#print $rdir;
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if ((not defined($rdir)) or $rdir eq '') {
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print("Please source sourceme-f1.sh!\n");
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exit();
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}
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# my $build_sbt = '
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# organization := "edu.berkeley.cs"
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#
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# version := "1.0"
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#
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# name := "hls_test_c"';
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#
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# $build_sbt=~ s/test_c/$func_name/g;
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# my $build_sbt_path= "$bm_path/"."build.sbt";
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# open BUILD, ">$build_sbt_path";
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# print BUILD $build_sbt;
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# close BUILD;
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my $verilog_file = "$dir/../verilog/$func_name".".v";
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my $line = undef;
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my @verilog_param = ();
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my @param_val = ();
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my @verilog_input = ();
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my @verilog_input_size = ();
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my @verilog_output = ();
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my @verilog_output_size = ();
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#my $m_axi_data_width = undef;
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#my $s_axi_data_width = undef;
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my @bus_names=();
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my @m_axi_data_widths = ();
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my $s_axi_data_width = undef;
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print "Parsing ".$verilog_file."\n";
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# parse the verilog file to get the info we need
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if(!open VERILOG, "$verilog_file"){
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print $!;
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} else {
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while(<VERILOG>){
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$line = $_;
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# Match AXI4 parameter
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if($line =~ m/parameter\s+(C_\S+) =\s+(.*);/){
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my $param = $1;
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my $val = $2;
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$param .="";
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if($param =~ m/C_M_AXI_(\S+)_DATA_WIDTH/){
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my $bus_name = lc $1;
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#$m_axi_data_width = $val;
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push(@bus_names, $bus_name);
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push(@m_axi_data_widths, $val);
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}
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if ($param eq "C_S_AXI_DATA_WIDTH") {
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$s_axi_data_width = $val;
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}
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push (@verilog_param, $param);
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push (@param_val, $val);
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} elsif($line =~ m/^\s*input\s+(.*)/){
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my $input = $1;
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#print "input:$input\n";
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if($input =~ m/\s*\[(.*):(.*)\]\s*(.*)\s*;/){
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my $end = $1;
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my $start = $2;
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my $input_name = $3;
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#print "here!"."$input_name\n";
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push (@verilog_input, $input_name);
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my $size = 0;
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if ($end =~ m/^\d+$/){
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$size = $end - $start + 1;
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$size = "".$size;
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} elsif($end =~m/(\S+) - 1/) {
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$size = $1;
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}
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push(@verilog_input_size, $size);
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}elsif ($input =~ m/\s*(.*)\s*;/){
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my $input_name = $1;
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#print "here!"."$input_name\n";
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push (@verilog_input, $input_name);
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push(@verilog_input_size, "1");
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}
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}elsif($line =~ m/^\s*output\s+(.*)/){
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my $output = $1;
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#print "output:$output\n";
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if($output =~ m/\s*\[(.*):(.*)\]\s*(.*)\s*;/){
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my $end = $1;
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my $start = $2;
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my $output_name = $3;
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#print "here!"."$output_name\n";
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push(@verilog_output, $output_name);
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my $size = 0;
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if ($end =~ m/^\d+$/){
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$size = $end - $start + 1;
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$size = "".$size;
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} elsif($end =~m/(\S+) - 1/) {
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$size = $1;
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}
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push(@verilog_output_size, $size);
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}elsif ($output =~ m/\s*(.*)\s*;/){
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my $output_name = $1;
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#print "here!"."$output_name\n";
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push (@verilog_output, $output_name);
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push(@verilog_output_size, "1");
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}
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}
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}
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print("Parameters: ");
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my $param_str = join ' ', @verilog_param;
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print $param_str."\n";
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print("Inputs: ");
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my $in_str = join ' ', @verilog_input;
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print $in_str."\n";
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print("Outputs: ");
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my $out_str = join ' ', @verilog_output;
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print $out_str."\n";
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}
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#creat scala folder
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my $scala_dir = "$dir/../scala";
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mkdir $scala_dir unless (-d $scala_dir);
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##############################################################################################################################
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if(@m_axi_data_widths < 1){
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push(@bus_names, "gmem_dummy");
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push(@m_axi_data_widths, 32);
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}
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if(not defined($s_axi_data_width)) {
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$s_axi_data_width=32
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}
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print "Generating BlackBox file ...\n";
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for( $i = 0; $i < @m_axi_data_widths; $i = $i + 1 ){
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print "m_axi_data_width_ $bus_names[$i]= $m_axi_data_widths[$i]\n";
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}
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print "s_axi_data_width = $s_axi_data_width\n";
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# should be under scala folder
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open BB, ">$scala_dir/$func_name"."_blackbox.scala";
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my $blackbox1 = "
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package hls_test_c
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import Chisel._
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.util._
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class test_c() extends BlackBox() {
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";
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$blackbox1 =~ s/test_c/$func_name/g;
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# Print parameters
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for( $i = 0; $i < @verilog_param; $i = $i + 1 ){
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$blackbox1 .= "val $verilog_param[$i] = $param_val[$i]\n";
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}
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print BB $blackbox1;
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print BB "\tval io = new Bundle {\n";
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my $bb_body = "";
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# now if the input name does not start with ap, we assume it is an arg
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my $ap_return = 0;
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my $ap_clk = 0;
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my $ap_rst = 0;
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my $ap_rst_n = 0;
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my @verilog_axi_io = ();
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for( $i = 0; $i < @verilog_input; $i = $i + 1 ){
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my $input_name = $verilog_input[$i];
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my $input_size = $verilog_input_size[$i];
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if ($input_name =~ m/^ap_clk$/){
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$ap_clk = 1;
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}
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elsif ($input_name =~ m/^ap_rst$/){
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$ap_rst = 1;
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}
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elsif ($input_name =~ m/^ap_rst_n$/){
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$ap_rst_n = 1;
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}
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elsif($input_name =~ m/^(m_axi|s_axi)\S+$/){
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push (@verilog_axi_io, $input_name);
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}
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print BB "\t\tval $input_name = ";
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if ($input_name =~ m/ap_clk(.*)/){
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print BB "Clock\(INPUT\)\n";
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}else{
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print BB "Bits\(INPUT, width = $input_size\)\n";
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}
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}
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for( $i = 0; $i < @verilog_output; $i = $i + 1 ){
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my $output_name = $verilog_output[$i];
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my $output_size = $verilog_output_size[$i];
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if ($output_name =~ m/ap_return(.*)/){
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$ap_return = 1;
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}
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elsif($output_name =~ m/^(m_axi|s_axi)\S+$/){
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push (@verilog_axi_io, $output_name);
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}
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print BB "\t\tval $output_name = ";
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print BB "Bits(OUTPUT, width = $output_size)\n";
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}
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print BB "\t}\n";
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print BB "}\n";
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close BB;
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##############################################################################################################################
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print "Generating Control file ...\n";
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open CT, ">$scala_dir/$func_name"."_accel.scala";
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#TODO Fix AXI4 params
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my $control1 = '
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package hls_test_c
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import chisel3._
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import chisel3.util._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem._
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class HLStest_cAXI (address: BigInt = 0x20000, beatBytes: Int = 8) (implicit p: Parameters) extends LazyModule {
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val numInFlight = 8
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';
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for( $i = 0; $i < @m_axi_data_widths; $i = $i + 1 ){
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$control1 .="
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val node_$bus_names[$i] = AXI4MasterNode(Seq(AXI4MasterPortParameters(
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masters = Seq(AXI4MasterParameters(
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name = \"axil_hub_mem_out_$i\",
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id = IdRange(0, numInFlight),
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aligned = true,
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maxFlight = Some(8)
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)),
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userBits = 0
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)
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))";
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}
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$control1 .='
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val slave_node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(address,0x4000-1)),
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regionType = RegionType.UNCACHED,
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supportsWrite = TransferSizes(1, beatBytes),
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supportsRead = TransferSizes(1, beatBytes),
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interleavedId = Some(0)
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)),
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beatBytes = beatBytes
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)))
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lazy val module = new HLStest_cAXIModule(this)
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}
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class HLStest_cAXIModule(outer: HLStest_cAXI) extends LazyModuleImp(outer) {
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//val (out, edge) = outer.node.out(0)
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val (slave_in, slave_edge) = outer.slave_node.in(0)
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val bId = Reg(UInt(32.W))
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val rId = Reg(UInt(32.W))
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val bb = Module(new test_c())
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';
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for( $i = 0; $i < @m_axi_data_widths; $i = $i + 1 ){
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$control1 .="
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val (out_$bus_names[$i], edge_$bus_names[$i]) = outer.node_$bus_names[$i].out(0)";
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}
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$control1 .= "\n";
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$control1 =~ s/s_axi_data_width/$s_axi_data_width/g;
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if ($ap_clk eq 1){
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$control1 .= "\tbb.io.ap_clk := clock\n";
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}
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if ($ap_rst eq 1){
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$control1 .= "\tbb.io.ap_rst := reset\n";
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}
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if ($ap_rst_n eq 1){
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$control1 .= "\tbb.io.ap_rst_n := !reset.toBool() \n";
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}
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$control1 =~ s/test_c/$func_name/g;
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print CT $control1;
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#TODO modify accelerator arg!
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my $control2 = '
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';
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# TODO Add support for multiple AXI buses
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# AXI Inputs Signals
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for( $i = 0; $i < @verilog_axi_io; $i = $i + 1 ){
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my $number = $i + 1;
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if ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|W|AR)READY$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := out_$bus_name.$type.ready\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(R|B)VALID$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := out_$bus_name.$type.valid\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(R)DATA$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := out_$bus_name.$type.bits.data\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(R)LAST$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := out_$bus_name.$type.bits.last\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(R|B)ID$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := out_$bus_name.$type.bits.id\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(R|B)RESP$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := out_$bus_name.$type.bits.resp\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(AW|W|AR)VALID$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := slave_in.$type.valid\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(AW|AR)ADDR$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := slave_in.$type.bits.addr\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(W)DATA$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := slave_in.$type.bits.data\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(W)STRB$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := slave_in.$type.bits.strb\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(R|B)READY$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tbb.io.$verilog_axi_io[$i] := slave_in.$type.ready\n";
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}
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}
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for( $i = 0; $i < @verilog_axi_io; $i = $i + 1 ){
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my $number = $i + 1;
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if ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|W|AR)VALID$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tout_$bus_name.$type.valid := bb.io.$verilog_axi_io[$i]\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(R|B)READY$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tout_$bus_name.$type.ready := bb.io.$verilog_axi_io[$i]\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)ADDR$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tout_$bus_name.$type.bits.addr := bb.io.$verilog_axi_io[$i]\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)ID$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tout_$bus_name.$type.bits.id := bb.io.$verilog_axi_io[$i]\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)LEN$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tout_$bus_name.$type.bits.len := bb.io.$verilog_axi_io[$i]\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)SIZE$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tout_$bus_name.$type.bits.size := bb.io.$verilog_axi_io[$i]\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)BURST$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tout_$bus_name.$type.bits.burst := bb.io.$verilog_axi_io[$i]\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)LOCK$/){
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my $bus_name = $1;
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my $type = lc $2;
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$control2 .= "\tout_$bus_name.$type.bits.lock := bb.io.$verilog_axi_io[$i]\n";
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}
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elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)CACHE$/){
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my $bus_name = $1;
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my $type = lc $2;
|
|
$control2 .= "\tout_$bus_name.$type.bits.cache := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)PROT$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tout_$bus_name.$type.bits.prot := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)QOS$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tout_$bus_name.$type.bits.qos := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(AW|AR)REGION$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\t//out_$bus_name.$type.bits.region := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(W)DATA$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tout_$bus_name.$type.bits.data := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(W)STRB$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tout_$bus_name.$type.bits.strb := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/m_axi_(.*)_(W)LAST$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tout_$bus_name.$type.bits.last := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(AW|W|AR)READY$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tslave_in.$type.ready := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(R|B)VALID$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tslave_in.$type.valid := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(R)DATA$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tslave_in.$type.bits.data := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
elsif ($verilog_axi_io[$i] =~ m/s_axi_(.*)_(R|B)RESP$/){
|
|
my $bus_name = $1;
|
|
my $type = lc $2;
|
|
$control2 .= "\tslave_in.$type.bits.resp := bb.io.$verilog_axi_io[$i]\n";
|
|
}
|
|
}
|
|
|
|
if ($ap_return eq 1){
|
|
$control2 = $control2."\tval ap_return = accel.io.ap.rtn\n";
|
|
}
|
|
$control2 .= "
|
|
// For AXI4lite, these two signals are always True
|
|
slave_in.r.bits.last := true.B
|
|
|
|
when(slave_in.aw.fire()){
|
|
bId := slave_in.aw.bits.id
|
|
}
|
|
|
|
when(slave_in.ar.fire()){
|
|
rId := slave_in.ar.bits.id
|
|
}
|
|
slave_in.r.bits.id := rId
|
|
slave_in.b.bits.id := bId
|
|
}
|
|
";
|
|
|
|
# TODO Fix the width here
|
|
$control2 .='
|
|
trait HasPeripheryHLStest_cAXI { this: BaseSubsystem =>
|
|
private val address = BigInt(base_addr)
|
|
private val axi_m_portName = "HLS-Accelerator-test_c-master"
|
|
private val axilite_s_portName = "HLS-Accelerator-test_c-slave"
|
|
|
|
//val accel_s_axi_width = s_axi_data_width
|
|
//val hls_test_c_accel = LazyModule(new HLStest_cAXI(address, sbus.beatBytes))
|
|
val hls_test_c_accel = LazyModule(new HLStest_cAXI(address, s_axi_data_width >> 3))
|
|
';
|
|
|
|
|
|
for( $i = 0; $i < @m_axi_data_widths; $i = $i + 1 ){
|
|
$control2 .="
|
|
sbus.fromPort(Some(axi_m_portName)) {
|
|
(TLWidthWidget($m_axi_data_widths[$i]>> 3 )
|
|
:= AXI4ToTL()
|
|
:= AXI4UserYanker(Some(8))
|
|
:= AXI4Fragmenter()
|
|
:= AXI4IdIndexer(1))
|
|
}:=* hls_test_c_accel.node_$bus_names[$i]
|
|
";
|
|
}
|
|
|
|
$control2 .='
|
|
hls_test_c_accel.slave_node :=* sbus.toFixedWidthPort(Some(axilite_s_portName)) {
|
|
(AXI4Buffer()
|
|
:= AXI4UserYanker()
|
|
//:= AXI4IdIndexer(params.idBits)
|
|
//:= AXI4Deinterleaver(sbus.blockBytes) // Assume there is no iterleaved requests, iterleaveId = Some(0)
|
|
:= TLToAXI4()
|
|
:= TLBuffer()
|
|
//:= TLWidthWidget(s_axi_data_width >> 3)
|
|
// Compared to TLWidthWidget, TLFragmenter saves the id info?
|
|
:= TLFragmenter(s_axi_data_width >> 3, 64, alwaysMin=true, holdFirstDeny=true))
|
|
}
|
|
}
|
|
|
|
trait HasPeripheryHLStest_cAXIImp extends LazyModuleImp {
|
|
val outer: HasPeripheryHLStest_cAXI
|
|
}';
|
|
|
|
$control2 =~ s/test_c/$func_name/g;
|
|
$control2 =~ s/base_addr/$func_base_addr/g;
|
|
$control2 =~ s/s_axi_data_width/$s_axi_data_width/g;
|
|
print CT $control2;
|
|
|