265 lines
9.7 KiB
Perl
265 lines
9.7 KiB
Perl
#!/usr/bin/perl
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use strict;
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use warnings;
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use JSON qw( decode_json );
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use Cwd;
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use File::Copy;
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my $dir = getcwd;
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sub generate_f1_scripts{
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my $rdir = $ENV{'RDIR'};
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if ((not defined($rdir)) or $rdir eq '') {
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print("Please source sourceme-f1-manager.sh!\n");
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exit();
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}
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my $cl_dir = $ENV{'CL_DIR'};
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#print $cl_dir;
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if ((not defined($cl_dir)) or $cl_dir eq '') {
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print("Please source sourceme-f1.sh!\n");
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exit();
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}
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# hash of all hls bm and its path
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my %bm_path = %{$_[0]};
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open EN_TCL, ">$cl_dir/build/scripts/encrypt.tcl";
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open SYN_TCL, ">$cl_dir/build/scripts/synth_cl_firesim.tcl";
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#my $bm_path = $rdir."/sim/target-rtl/firechip/hls_$file_name"."_$func_name";
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my $encrypt_tcl = '# TODO:
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# Add check if CL_DIR and HDK_SHELL_DIR directories exist
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# Add check if /build and /build/src_port_encryption directories exist
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# Add check if the vivado_keyfile exist
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set HDK_SHELL_DIR $::env(HDK_SHELL_DIR)
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set HDK_SHELL_DESIGN_DIR $::env(HDK_SHELL_DESIGN_DIR)
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set CL_DIR $::env(CL_DIR)
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set TARGET_DIR $CL_DIR/build/src_post_encryption
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set UNUSED_TEMPLATES_DIR $HDK_SHELL_DESIGN_DIR/interfaces
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# Remove any previously encrypted files, that may no longer be used
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if {[llength [glob -nocomplain -dir $TARGET_DIR *]] != 0} {
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eval file delete -force [glob $TARGET_DIR/*]
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}
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#---- Developr would replace this section with design files ----
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## Change file names and paths below to reflect your CL area. DO NOT include AWS RTL files.
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file copy -force $CL_DIR/design/cl_firesim_defines.vh $TARGET_DIR
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file copy -force $CL_DIR/design/cl_firesim_generated_defines.vh $TARGET_DIR
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file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_inst.v $TARGET_DIR
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file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_ports.v $TARGET_DIR
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file copy -force $CL_DIR/design/ila_files/firesim_ila_insert_wires.v $TARGET_DIR
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file copy -force $CL_DIR/design/cl_id_defines.vh $TARGET_DIR
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file copy -force $CL_DIR/design/cl_firesim.sv $TARGET_DIR
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file copy -force $CL_DIR/design/cl_firesim_generated.sv $TARGET_DIR
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file copy -force $CL_DIR/../common/design/cl_common_defines.vh $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_apppf_irq_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_cl_sda_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_a_b_d_template.inc $TARGET_DIR
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# we will use ddr_c unlike hello world:
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#file copy -force $UNUSED_TEMPLATES_DIR/unused_ddr_c_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_dma_pcis_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_pcim_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_sh_bar1_template.inc $TARGET_DIR
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file copy -force $UNUSED_TEMPLATES_DIR/unused_flr_template.inc $TARGET_DIR
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';
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while(my($bm, $path) = each %bm_path) {
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system("mkdir -p $cl_dir/design/$bm");
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system("cp $path/src/main/verilog/* $cl_dir/design/$bm");
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#my $copy_hls_src = "set src_list [glob $path/src/main/verilog/*]\n".'foreach src $src_list {
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my $copy_hls_src = "set src_list [glob \$CL_DIR/design/$bm/*]\n".'foreach src $src_list {
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file copy -force $src $TARGET_DIR
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}
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';
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#print($copy_hls_src);
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$encrypt_tcl .= $copy_hls_src;
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}
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$encrypt_tcl .= '# Make sure files have write permissions for the encryption
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exec chmod +w {*}[glob $TARGET_DIR/*]
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set TOOL_VERSION $::env(VIVADO_TOOL_VERSION)
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set vivado_version [string range [version -short] 0 5]
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puts "AWS FPGA: VIVADO_TOOL_VERSION $TOOL_VERSION"
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puts "vivado_version $vivado_version"
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# encrypt .v/.sv/.vh/inc as verilog files
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encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_keyfile_2017_4.txt -lang verilog [glob -nocomplain -- $TARGET_DIR/*.{v,sv}] [glob -nocomplain -- $TARGET_DIR/*.vh] [glob -nocomplain -- $TARGET_DIR/*.inc]
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# encrypt *vhdl files
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encrypt -k $HDK_SHELL_DIR/build/scripts/vivado_vhdl_keyfile_2017_4.txt -lang vhdl -quiet [ glob -nocomplain -- $TARGET_DIR/*.vhd? ]
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';
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print EN_TCL $encrypt_tcl;
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close EN_TCL;
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my @tcl_files =();
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# Find the HLS generated IP tcl to source
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while(my($bm, $path) = each %bm_path) {
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#chdir($path.'/src/main/verilog') or die "$!";
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chdir("$cl_dir/design/$bm") or die "$!";
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#my @local_tcl_files = map { Cwd::abs_path($_) } glob "*.tcl";
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my @local_tcl_files = map { "\$CL_DIR/design/$bm/".$_ } glob "*.tcl";
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push(@tcl_files, @local_tcl_files);
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}
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my $synth_cl_firesim = '
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########################################
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## Generate ILA based on Recipe
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########################################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling firesim_ila_insert_vivado.tcl to generate ILAs from developer\'s specified recipe.";
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source $CL_DIR/design/ila_files/firesim_ila_insert_vivado.tcl
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#Param needed to avoid clock name collisions
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set_param sta.enableAutoGenClkNamePersistence 0
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set CL_MODULE $CL_MODULE
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set VDEFINES $VDEFINES
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create_project -in_memory -part [DEVICE_TYPE] -force
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########################################
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## Generate clocks based on Recipe
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########################################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Calling aws_gen_clk_constraints.tcl to generate clock constraints from developer\'s specified recipe.";
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';
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foreach my $tcl_file (@tcl_files) {
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$synth_cl_firesim .="source $tcl_file\n";
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}
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$synth_cl_firesim .= 'source $HDK_SHELL_DIR/build/scripts/aws_gen_clk_constraints.tcl
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#############################
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## Read design files
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#############################
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#Convenience to set the root of the RTL directory
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set ENC_SRC_DIR $CL_DIR/build/src_post_encryption
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Reading developer\'s Custom Logic files post encryption.";
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#---- User would replace this section -----
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# Reading the .sv and .v files, as proper designs would not require
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# reading .v, .vh, nor .inc files
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read_verilog -sv [glob $ENC_SRC_DIR/*.?v]
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read_verilog -sv [glob $ENC_SRC_DIR/*.v]
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set v_list [glob $ENC_SRC_DIR/*.v]
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puts $v_list
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#---- End of section replaced by User ----
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puts "AWS FPGA: Reading AWS Shell design";
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#Read AWS Design files
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read_verilog -sv [ list \
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$HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
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$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sync.v \
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$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/flop_ccf.sv \
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$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/ccf_ctl.v \
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$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/sh_ddr.sv \
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$HDK_SHELL_DESIGN_DIR/lib/lib_pipe.sv \
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$HDK_SHELL_DESIGN_DIR/lib/bram_2rw.sv \
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$HDK_SHELL_DESIGN_DIR/lib/flop_fifo.sv \
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$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_acc_axl.sv \
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$HDK_SHELL_DESIGN_DIR/sh_ddr/synth/mgt_gen_axl.sv \
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$HDK_SHELL_DESIGN_DIR/interfaces/cl_ports.vh
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]
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puts "AWS FPGA: Reading IP blocks";
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#Read IP for axi register slices
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read_ip [ list \
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$HDK_SHELL_DESIGN_DIR/ip/src_register_slice/src_register_slice.xci \
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$HDK_SHELL_DESIGN_DIR/ip/dest_register_slice/dest_register_slice.xci \
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$HDK_SHELL_DESIGN_DIR/ip/axi_register_slice/axi_register_slice.xci \
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$HDK_SHELL_DESIGN_DIR/ip/axi_register_slice_light/axi_register_slice_light.xci
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]
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#Read IP for virtual jtag / ILA/VIO
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read_ip [ list \
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$HDK_SHELL_DESIGN_DIR/ip/ila_0/ila_0.xci\
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$HDK_SHELL_DESIGN_DIR/ip/cl_debug_bridge/cl_debug_bridge.xci \
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$HDK_SHELL_DESIGN_DIR/ip/ila_vio_counter/ila_vio_counter.xci \
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$HDK_SHELL_DESIGN_DIR/ip/vio_0/vio_0.xci \
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$HDK_SHELL_DESIGN_DIR/ip/axi_clock_converter_0/axi_clock_converter_0.xci \
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$CL_DIR/ip/axi_clock_converter_dramslim/axi_clock_converter_dramslim.xci \
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$CL_DIR/ip/axi_clock_converter_oclnew/axi_clock_converter_oclnew.xci \
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$CL_DIR/ip/axi_clock_converter_512_wide/axi_clock_converter_512_wide.xci \
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$CL_DIR/ip/axi_dwidth_converter_0/axi_dwidth_converter_0.xci \
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$CL_DIR/ip/firesim_ila_ip/ila_firesim_0/ila_firesim_0.xci
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]
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# Additional IPs that might be needed if using the DDR
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read_ip [ list \
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$HDK_SHELL_DESIGN_DIR/ip/ddr4_core/ddr4_core.xci
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]
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read_bd [ list \
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$HDK_SHELL_DESIGN_DIR/ip/cl_axi_interconnect/cl_axi_interconnect.bd
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]
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puts "AWS FPGA: Reading AWS constraints";
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#Read all the constraints
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#
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# cl_clocks_aws.xdc - AWS auto-generated clock constraint. ***DO NOT MODIFY***
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# cl_ddr.xdc - AWS provided DDR pin constraints. ***DO NOT MODIFY***
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# cl_synth_user.xdc - Developer synthesis constraints.
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read_xdc [ list \
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$CL_DIR/build/constraints/cl_clocks_aws.xdc \
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$HDK_SHELL_DIR/build/constraints/cl_ddr.xdc \
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$HDK_SHELL_DIR/build/constraints/cl_synth_aws.xdc \
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$CL_DIR/build/constraints/cl_synth_user.xdc
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]
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# FireSim custom clocking
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source $CL_DIR/build/scripts/synth_firesim_clk_wiz.tcl
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#Do not propagate local clock constraints for clocks generated in the SH
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set_property USED_IN {synthesis implementation OUT_OF_CONTEXT} [get_files cl_clocks_aws.xdc]
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set_property PROCESSING_ORDER EARLY [get_files cl_clocks_aws.xdc]
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########################
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# CL Synthesis
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########################
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthesis.";
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update_compile_order -fileset sources_1
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puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
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eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive -retiming]
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set failval [catch {exec grep "FAIL" failfast.csv}]
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if { $failval==0 } {
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puts "AWS FPGA: FATAL ERROR--Resource utilization error; check failfast.csv for details"
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exit 1
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}
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puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.";
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write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp
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close_project
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#Set param back to default value
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set_param sta.enableAutoGenClkNamePersistence 1
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';
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print SYN_TCL $synth_cl_firesim;
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close SYN_TCL;
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}
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1;
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