77 lines
2.7 KiB
Python
77 lines
2.7 KiB
Python
import subprocess
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import logging
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from .. import util
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logger = logging.getLogger(__name__)
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logger.setLevel(logging.NOTSET)
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def run_bm_sw(accel_conf, simulator, bm_sw_path):
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logger.info("\t\tRunning {} Simulation for {}".format(simulator, bm_sw_path))
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sims_dir = accel_conf.sims_dir / simulator
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cmd = "simv-chipyard-{}-debug {}".format(accel_conf.CONFIG, str(bm_sw_path))
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logger.info("\t\tCommand: {}".format(cmd))
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cmd_arr = cmd.split()
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subprocess.check_call(cmd_arr, cwd=sims_dir)
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def compile_sim_cmd(accel_conf, simulator, cmd="", check_call=True):
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clean_str = "";
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sims_dir = accel_conf.sims_dir / simulator
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cmd = "make {} CONFIG={}".format(cmd, accel_conf.CONFIG)
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logger.info("\t\tCompiling {} Simulation in {}".format(simulator, sims_dir))
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logger.info("\t\tCommand: {}".format(cmd))
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cmd_arr = cmd.split()
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try:
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subprocess.check_call(cmd_arr, cwd=sims_dir)
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except Exception:
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if check_call:
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raise()
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def run_sim(accel_conf, simulator, subtask, bm_sw_path=None):
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if subtask is None:
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compile_sim_cmd(accel_conf, simulator, 'clean')
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compile_sim_cmd(accel_conf, simulator, 'debug', False)
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append_verilog_to_top_v(accel_conf, simulator)
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compile_sim_cmd(accel_conf, simulator, 'debug')
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else:
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if subtask == 'clean':
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compile_sim_cmd(accel_conf, simulator, 'clean')
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elif subtask == 'debug':
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compile_sim_cmd(accel_conf, simulator, 'debug')
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elif subtask == 'append_verilog':
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append_verilog_to_top_v(accel_conf, simulator)
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elif subtask == 'run_bm_sw':
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if bm_sw_path is None:
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import argparse
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raise argparse.ArgumentError("Please specify software baremetal binary path with --swfile/-p!")
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run_bm_sw(accel_conf, simulator, bm_sw_path)
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else:
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raise NotImplementedError()
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def append_verilog_to_top_v(accel_conf, simulator):
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top_v_prefix = "chipyard.TestHarness.{}".format(accel_conf.CONFIG)
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top_v_file = "{}.top.v".format(top_v_prefix)
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top_v_path = accel_conf.sims_dir / simulator / "generated-src" / top_v_prefix / top_v_file
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logger.info("\t\tAppend Verilog Files to {}".format(top_v_path))
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for accel in accel_conf.rocc_accels + accel_conf.tl_accels:
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verilog_dir = accel.verilog_dir
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# list all verilog file
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verilog_files = list(verilog_dir.glob('**/*.v'))
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for verilog_file in verilog_files:
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util.append_to_file(verilog_file, top_v_path)
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def run_vcs(accel_conf, subtask, bm_sw_path):
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run_sim(accel_conf, 'vcs', subtask, bm_sw_path)
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def run_verilator(accel_conf, subtask, bm_sw_path):
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run_sim(accel_conf, 'verilator', subtask, bm_sw_path)
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