76 lines
2.1 KiB
Python
76 lines
2.1 KiB
Python
from __future__ import print_function
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import re
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import random
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import logging
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import json
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import os
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import shutil
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import errno
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import subprocess
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from string import Template
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from .. import util
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from . import run_hls
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from . import generate_chisel
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from . import generate_build_sbt
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from . import generate_config
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logger = logging.getLogger(__name__)
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logger.setLevel(logging.NOTSET)
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def init_proj_dir(accel):
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"""Init project directory for accel"""
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dirs = [accel.c_dir, accel.scala_dir, accel.verilog_dir]
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for directory in dirs:
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if not directory.exists():
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util.mkdir_p(directory)
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def cp_src(accel):
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"""Copy src files"""
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for src_path in accel.srcs:
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shutil.copy(src_path, accel.c_dir)
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logger.info("\t\tCopy\t{} to {}".format(src_path, accel.c_dir))
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def init_accel(accel_conf):
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"""Init project directories for accel SoC"""
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for accel in accel_conf.rocc_accels + accel_conf.tl_accels:
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logger.info("\tInitialize {}:".format(accel.prefix_id))
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init_proj_dir(accel)
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cp_src(accel)
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def rm_accel(accel_conf):
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"""Remove directories for the accel SoC"""
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shutil.rmtree(accel_conf.hw_accel_dir)
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def generate_hw(accel_conf, subtask):
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"""Generate hardware SoC """
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if subtask is None:
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logger.info("Initialize Generated Hardware Repository {}".format(accel_conf.hw_accel_dir))
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init_accel(accel_conf)
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run_hls.run_hls(accel_conf)
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generate_chisel.generate_chisel(accel_conf)
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generate_build_sbt.generate_build_sbt(accel_conf)
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generate_config.generate_config(accel_conf)
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else:
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if subtask == "hls":
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run_hls.run_hls(accel_conf)
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elif subtask == "chisel":
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generate_chisel.generate_chisel(accel_conf)
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elif subtask == "build_sbt":
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generate_build_sbt.generate_build_sbt(accel_conf)
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elif subtask == "config":
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generate_config.generate_config(accel_conf)
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else:
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raise NotImplementedError()
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def clean_hw(accel_conf):
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"""Clean hardware SoC Repo """
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rm_accel(accel_conf)
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