52 lines
1.5 KiB
Python
52 lines
1.5 KiB
Python
import pathlib
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import shutil
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import collections
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import logging
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import argparse
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from string import Template
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import re
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from .. import util
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logger = logging.getLogger(__name__)
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logger.setLevel(logging.DEBUG)
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def generate_build_sbt(accel_conf):
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logger.info("Generating build.sbt file ...")
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accel_template = Template("""
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lazy val ${SOC_NAME} = (project in file("generators/${SOC_NAME}"))
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.dependsOn(boom, testchipip, hwacha, sifive_blocks, sifive_cache${ACCELS})
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.settings(chiselSettings)
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.settings(commonSettings)
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""")
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bm_template = Template("""
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lazy val ${ACCEL} = (project in file("${DIR}"))
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.dependsOn(rocketchip, testchipip, midasTargetUtils, icenet)
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.settings(chiselSettings)
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.settings(commonSettings)
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""")
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accel_config_str = ""
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bms_str = ""
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for accel in accel_conf.rocc_accels + accel_conf.tl_accels:
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d = {'ACCEL': 'hls_' + accel.name, 'DIR': accel.dir}
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bms_str += ", hls_"+ accel.name
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accel_config_str += bm_template.substitute(d)
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d = {'SOC_NAME': accel_conf.accel_name, 'ACCELS': bms_str}
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accel_config_str += accel_template.substitute(d)
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template_path = util.getOpt('template-dir') / 'build_sbt_template'
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hls_soc_name_str = accel_conf.accel_name
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config_dict = {
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'HLS_SOC_NAME': hls_soc_name_str,
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'HLS_SOC_CONFIG': accel_config_str
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}
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chipyard_dir = util.getOpt('chipyard-dir')
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sbt_path = chipyard_dir / 'build.sbt'
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util.generate_file(template_path, config_dict, sbt_path)
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logger.info("\t\tGenerate build.sbt: {}".format(sbt_path))
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