8919f534e0
Add example makefile and software code
2023-09-23 18:27:39 -07:00
53f2c42017
Fix the wrapper generation bug
2023-09-23 16:00:20 -07:00
bac5502839
Fix Makefile name to write to
2023-09-16 08:12:57 -07:00
cf59a5a4f3
Generate Makefile in generateSW
2023-09-16 08:12:18 -07:00
17806d5dba
Merge branch 'python-dev-new' of github.com:hqjenny/centrifuge into python-dev-new
2023-09-09 07:56:29 -07:00
57f83750b6
Fix one arg sw generation path
2023-09-09 07:56:11 -07:00
4dc78f31be
fix missing ap_return key value
2023-09-09 07:19:19 -07:00
1288e88469
Fix error for constant input
2023-09-02 09:53:37 -07:00
043f562275
Update tilelink converter
2023-07-31 18:14:19 -07:00
da4b8d6a57
Remove TOP from make config
2023-06-07 10:22:46 -07:00
3887cac15c
Add logging info for sw wrapper
2023-06-01 14:24:44 -07:00
31bcb9f64c
working version
2023-04-03 18:37:48 -07:00
ae68d83f45
new fixes
2023-03-27 18:43:28 -07:00
20ba20161d
fixing some errors
2023-03-26 22:11:36 -07:00
676b5f6f03
Previous debugging changes
2023-03-06 18:22:13 -08:00
b2b2f8e584
Initial fixes to generating build.sbt
2023-02-27 18:43:54 -08:00
475af86086
Merge branch 'generateChisel' of github.com:hqjenny/centrifuge into generateChisel
2022-10-03 17:21:34 -07:00
3159550d50
Add exception handling to compiler sim cmd
2022-10-03 17:21:28 -07:00
662ec8d47e
Add FireSim compile/run scripts
2020-03-31 11:34:56 +00:00
04ad9ebeb5
Fix Chisel generation bug; Add VCS Simulation Commands
2020-03-30 02:43:16 -07:00
6b5429c9eb
Fix hw generation bugs including not allowing understore in Config name; Fail to add Parameteres for HLS configs
2020-03-28 05:59:37 -07:00
968f89061b
Add code to update verilog file to make it work in chipyard simulators
2020-03-28 05:39:55 -07:00
e40c138316
Add generate config; Add argparse help and options
2020-03-19 08:15:26 -07:00
c02423b576
Add generate build sbt script; renam run_chisel script
2020-03-18 04:20:45 -07:00
987f0b3e9a
Add chisel generation code for tl
2020-03-17 03:23:46 -07:00
d05c2998d8
Add chisel generation code for rocc
2020-03-16 04:20:26 -07:00
428e15d97d
Merge branch 'python-dev' of github.com:hqjenny/centrifuge into python-dev
2020-02-11 13:48:16 -08:00
fe03da65ca
Change the hw prefix generation
2020-02-11 13:48:10 -08:00
5ecaac0881
Generate wrapper succesfully generates wrappers. I haven't verified that
...
the generated wrappers themselves work (but this was tested a while ago
so they should be close). This will require a slight change to
generate_hw to rename the verilog outputs to use accel.name to name
stuff.
2020-02-11 15:05:20 -05:00
249ed20178
Add in wrapper generation code (build_sw command). Previous versions
...
were tested, but this instance hasn't been yet.
2020-02-11 14:25:43 -05:00
0b9dce56de
Fix python version, use pathlib and mv template folder
2020-02-08 02:04:44 -08:00
410eda4cc8
Add HLS scripts
2020-02-05 15:56:54 -08:00
6216088a93
Refactor around a pkg directory. Tested configuration system.
2020-02-04 20:04:59 -05:00
Jenny Huang