Add args to generate soc
This commit is contained in:
Jenny Huang
parent
b142ed7779
commit
a3047c5763
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@ -14,6 +14,7 @@ if ((not defined($rdir)) or $rdir eq '') {
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sub generate_accel{
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my @accel_tuples= @{$_[0]};
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my %tasks = %{$_[1]};
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foreach my $accel_tuple_ref (@accel_tuples) {
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print($accel_tuple_ref);
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@ -58,20 +59,31 @@ sub generate_accel{
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print("$dir\n");
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#next;
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system("perl run_hls.pl ${PGM} ${FUNC} $prefix");
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if ($tasks{'accel_hls'}){
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system("perl run_hls.pl ${PGM} ${FUNC} $prefix");
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}
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if ($is_rocc) {
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system("cp -H $RDIR/tools/centrifuge/scripts/run_chisel.pl $bm_path_c");
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system("cp -H $RDIR/tools/centrifuge/scripts/generate_wrapper.pl $bm_path_c");
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system("perl run_chisel.pl ${PGM} ${FUNC} $prefix");
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system("perl generate_wrapper.pl ${PGM} ${FUNC} $idx_addr $prefix");
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if ($tasks{'accel_chisel'}){
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system("perl run_chisel.pl ${PGM} ${FUNC} $prefix");
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}
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if ($tasks{'accel_sw'}){
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system("perl generate_wrapper.pl ${PGM} ${FUNC} $idx_addr $prefix");
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}
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#system("make clean");
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#system("make CUSTOM_INST=1");
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} else {
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system("cp -H $RDIR/tools/centrifuge/scripts/run_chisel_tl.pl $bm_path_c");
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system("cp -H $RDIR/tools/centrifuge/scripts/generate_wrapper_tl.pl $bm_path_c");
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system("perl run_chisel_tl.pl ${PGM} ${FUNC} $idx_addr $prefix");
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system("perl generate_wrapper_tl.pl ${PGM} ${FUNC} $idx_addr $prefix");
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if ($tasks{'accel_chisel'}){
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system("perl run_chisel_tl.pl ${PGM} ${FUNC} $idx_addr $prefix");
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}
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if ($tasks{'accel_sw'}){
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system("perl generate_wrapper_tl.pl ${PGM} ${FUNC} $idx_addr $prefix");
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}
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#system("make clean");
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#system("make CUSTOM_DRIVER=1");
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}
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@ -3,18 +3,20 @@ use strict;
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use warnings;
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use Cwd;
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use File::Copy;
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use File::Path 'rmtree';
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my $dir = getcwd;
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################# Parse Arguments ####################
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my $json_fn = $ARGV[0];
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my $soc_name = $json_fn;
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$soc_name =~ s/.json//;
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my $rdir = $ENV{'RDIR'};
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my $postfix="";
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my $task = $ARGV[1];
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my $postfix="";
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my $num_args = $#ARGV + 1;
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if ($num_args > 1) {
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$postfix= $ARGV[1];
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if ($num_args > 2) {
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$postfix= $ARGV[2];
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}
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if ((not defined($rdir)) or $rdir eq '') {
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@ -26,7 +28,76 @@ if (not defined($json_fn)){
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print("Please specify a json config file\!\n");
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exit();
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}
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my $soc_name = $json_fn;
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$soc_name =~ s/.json//;
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my $arg_options = "Options:
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all -- Generate all HW/SW interfaces,configs, and scripts for the accelerator SoC
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accel -- Rerun accelerator HW/SW interface generation
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accel_hls -- Rerun HLS generation
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accel_chisel -- Rerun chisel wrapper generation (triggers accel_hls to run)
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accel_sw -- Rerun C wrapper generation (triggers accel_hls to run)
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build_sbt -- Regenerate build.sbt
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config -- Regenerate HLSConfig.scala file in examples and firechip
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f1_scripts -- Regenerate scripts for including HLS generated Verilog in FireSim
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xsim_scripts -- Regenerate scripts for including HLS generated Verilog in FireSim XSim
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vcs_scripts -- Regenerate vcs imulation
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verilator_scripts -- Regenerate verilator imulation
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clean -- Delete accelerator directory
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";
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my @valid_task_list = qw(all accel accel_hls accel_chisel accel_sw build_sbt config f1_scripts xsim_scripts vcs_scripts verilator_scripts clean);
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if (not defined($task) or not grep( /^$task$/, @valid_task_list)){
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print("Please specify a task\!\n");
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print($arg_options);
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exit();
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}
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if ($task eq 'clean') {
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rmtree(["$rdir/generators/$soc_name/"]);
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exit();
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}
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my @task_list = ();
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my @accel_task_list = qw(accel accel_hls accel_chisel accel_sw);
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if ($task eq 'all') {
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push (@task_list, @accel_task_list);
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push (@task_list, qw(build_sbt config f1_scripts xsim_scripts vcs_scripts));
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} elsif ($task eq 'accel') {
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push (@task_list, @accel_task_list);
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} elsif ($task eq 'accel_hls') {
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push (@task_list, qw(accel accel_hls));
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} elsif ($task eq 'accel_chisel') {
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push (@task_list, qw(accel accel_hls accel_chisel));
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} elsif ($task eq 'accel_sw') {
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push (@task_list, qw(accel accel_hls accel_sw));
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} elsif ($task eq 'build_sbt') {
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push (@task_list, qw(build_sbt));
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} elsif ($task eq 'config') {
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push (@task_list, qw(config));
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} elsif ($task eq 'f1_scripts') {
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push (@task_list, @accel_task_list);
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push (@task_list, qw(f1_scripts));
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} elsif ($task eq 'xsim_scripts') {
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push (@task_list, @accel_task_list);
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push (@task_list, qw(xsim_scripts));
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} elsif ($task eq 'vcs_scripts') {
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push (@task_list, @accel_task_list);
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push (@task_list, qw(vcs_scripts));
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} elsif ($task eq 'verilator_scripts') {
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push (@task_list, @accel_task_list);
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push (@task_list, qw(verilator_scripts));
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}
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my %tasks = ();
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foreach my $task (@valid_task_list) {
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$tasks{$task} = 0;
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}
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foreach my $task (@task_list) {
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$tasks{$task} = 1
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}
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################# Run ####################
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my $DESIGN='FireSimTopWithHLS';
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my $TARGET_CONFIG='HLSFireSimRocketChipConfig';
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my $PLATFORM_CONFIG='BaseF1Config_F90MHz';
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@ -95,32 +166,48 @@ foreach my $TLL2_accel (@TLL2_accels){
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}
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# Generate the verilog and chisel code
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generate_accel(\@Accel_tuples);
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if ($tasks{'accel'}){
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generate_accel(\@Accel_tuples, \%tasks);
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# SW
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# Copy Makefile Templates
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system("cp $scripts_dir/sw_aux/makefiles/* $rdir/generators/$soc_name/");
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}
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# Generate build.sbt under firesim/sim
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generate_build_sbt($soc_name, \%hls_bm);
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if ($tasks{'build_sbt'}){
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generate_build_sbt($soc_name, \%hls_bm);
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}
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# Generate HLSConfig file for RoCC Accelerators
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generate_config(\@RoCC_names, \@TLL2_names, $postfix);
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if ($tasks{'config'}){
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generate_config(\@RoCC_names, \@TLL2_names, $postfix);
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}
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# F1
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generate_f1_scripts(\%hls_bm);
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generate_xsim_scripts(\%hls_bm);
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compile_xsim_libs($postfix, "clean", 0);
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#compile_replace_rtl($postfix, "clean", 0);
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print_xsim_cmd($postfix, 0);
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if ($tasks{'f1_scripts'}){
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generate_f1_scripts(\%hls_bm);
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}
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if ($tasks{'xsim_scripts'}){
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generate_xsim_scripts(\%hls_bm);
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}
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if ($tasks{'f1_scripts'} or $tasks{'xsim_scripts'}){
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compile_replace_rtl($postfix, "clean", 0);
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}
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if ($tasks{'xsim_scripts'}){
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compile_xsim_libs($postfix, "clean", 0);
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print_xsim_cmd($postfix, 0);
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}
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# Ax machines
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# compile_vcs("clean");
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# copy_verilog(\%hls_bm, "$rdir/sims/vcs/generated-src/example.TestHarness.HLSRocketConfig/example.TestHarness.HLSRocketConfig.top.v");
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# compile_vcs("");
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if ($tasks{'vcs_scripts'}){
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compile_vcs("clean");
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copy_verilog(\%hls_bm, "$rdir/sims/vcs/generated-src/example.TestHarness.$CONFIG/example.TestHarness.$CONFIG.top.v");
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compile_vcs("");
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}
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# compile_verilator("clean");
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# copy_verilog(\%hls_bm, "$rdir/sims/verilator/generated-src/example.TestHarness.HLSRocketConfig/example.TestHarness.HLSRocketConfig.top.v");
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# compile_verilator("");
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# SW
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# Copy Makefile Templates
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system("cp $scripts_dir/sw_aux/makefiles/* $rdir/generators/$soc_name/");
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if ($tasks{'verilator_scripts'}){
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compile_verilator("clean");
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copy_verilog(\%hls_bm, "$rdir/sims/verilator/generated-src/example.TestHarness.$CONFIG/example.TestHarness.$CONFIG.top.v");
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compile_verilator("");
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}
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sub print_xsim_cmd{
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my $postfix= $_[0];
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