Add dprv connection for new Chipyard HellaCacheIO
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3887cac15c
commit
7c0a7f7177
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@ -60,6 +60,9 @@ io.resp.bits.data := result
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io.busy := busy
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io.busy := busy
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cmd.ready := rdy
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cmd.ready := rdy
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// Set the HellaCache req privilege to rocc command privilege
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io.mem.req.bits.dprv := io.cmd.bits.status.dprv
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//===== Begin Accelerator =====
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//===== Begin Accelerator =====
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val accel = Module(new HLS${FUNC}Blackbox())
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val accel = Module(new HLS${FUNC}Blackbox())
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@ -13,7 +13,8 @@ void print_vec(int* vec, int length){
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}
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}
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int main () {
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int main () {
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int length_a[LENGTH + 1], b_c[LENGTH + LENGTH];
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int length_a[LENGTH + 1] __attribute__((aligned(64)));
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int b_c[LENGTH + LENGTH] __attribute__((aligned(64)));
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//int a[LENGTH], b[LENGTH], c[LENGTH];
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//int a[LENGTH], b[LENGTH], c[LENGTH];
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int length = LENGTH;
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int length = LENGTH;
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length_a[0] = length;
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length_a[0] = length;
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@ -23,6 +24,7 @@ int main () {
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b_c[i] = i + 5;
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b_c[i] = i + 5;
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}
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}
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printf("length_a ptr: %X", length_a);
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uint64_t begin, end, dur;
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uint64_t begin, end, dur;
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begin = read_cycle();
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begin = read_cycle();
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vadd(length_a, b_c);
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vadd(length_a, b_c);
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