Previous debugging changes

deploy/pkg/buildaccel/generate_build_sbt.py

@@ -17,12 +17,14 @@ def generate_build_sbt(accel_conf):
     accel_template = Template("""
 lazy val ${SOC_NAME} = (project in file("generators/${SOC_NAME}"))
   .dependsOn(boom, testchipip, hwacha, sifive_blocks, sifive_cache${ACCELS})
+  .settings(chiselSettings)
   .settings(commonSettings)
 """)
 
     bm_template = Template("""
 lazy val ${ACCEL} = (project in file("${DIR}"))
   .dependsOn(rocketchip, testchipip, midasTargetUtils, icenet)
+  .settings(chiselSettings)
   .settings(commonSettings)
 """)
 

deploy/pkg/buildaccel/generate_chisel.py

@@ -205,7 +205,7 @@ def generate_opt_ap_signals(inputs, outputs):
     if 'ap_clk' in list(inputs.keys()):
         ret_str += "    bb.io.ap_clk := clock\n"
     if 'ap_rst_n' in list(inputs.keys()):
-        ret_str += "    bb.io.ap_rst_n := !reset.toBool()\n"
+        ret_str += "    bb.io.ap_rst_n := !reset.asBool()\n"
     return ret_str
 
 

deploy/support/templates/HLSConfig_scala_template

@@ -52,4 +52,4 @@ class HLSRocketConfig extends Config(
     new freechips.rocketchip.subsystem.WithNoSlavePort ++          // no top-level MMIO slave port (overrides default set in rocketchip)
     new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
     new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
-    new freechips.rocketchip.system.BaseConfig)
+    new chipyard.config.AbstractConfig)

deploy/support/templates/ap_bus_scala_template

@@ -14,13 +14,11 @@ class ApBusReq(dataWidth:Int, addrWidth:Int) extends Bundle{
   val address     = UInt(OUTPUT, width = addrWidth)
   val dataout     = UInt(OUTPUT, width = dataWidth)
   val size        = UInt(OUTPUT, width = addrWidth)
-  override def cloneType: this.type = new ApBusReq(dataWidth, addrWidth).asInstanceOf[this.type]
 }
 
 //Response Packet Format
 class ApBusRsp(dataWidth:Int) extends Bundle{
   val datain      = UInt(INPUT , width = dataWidth)
-  override def cloneType: this.type = new ApBusRsp(dataWidth).asInstanceOf[this.type]
 }
 
 class ApBusIO(dataWidth:Int = 64, addrWidth:Int = 32) extends Bundle{
@@ -32,7 +30,6 @@ class ApBusIO(dataWidth:Int = 64, addrWidth:Int = 32) extends Bundle{
   val rsp = new ApBusRsp(dataWidth)
   val rsp_empty_n = Bool(INPUT )
   val rsp_read    = Bool(OUTPUT)
-  override def cloneType: this.type = new ApBusIO(dataWidth, addrWidth).asInstanceOf[this.type]
 }
 
 class ApCtrlIO(dataWidth:Int = 64) extends Bundle{
@@ -43,5 +40,4 @@ class ApCtrlIO(dataWidth:Int = 64) extends Bundle{
   val idle   = Bool(OUTPUT)
   val ready  = Bool(OUTPUT)
   val rtn    = UInt(OUTPUT, width = dataWidth)
-  override def cloneType: this.type = new ApCtrlIO(dataWidth).asInstanceOf[this.type]
 }

deploy/support/templates/chisel_rocc_accel_scala_template

@@ -40,7 +40,7 @@ val rs2_unbuffered = cmd.bits.rs2
 val idle :: working :: Nil = Enum(UInt(),2)
 val state = Reg(init=idle)
 
-when(reset.toBool){
+when(reset.asBool){
   bufferedCmd.inst.funct := 0.asUInt(7.W)
   bufferedCmd.inst.rs1 := 0.asUInt(5.W)
   bufferedCmd.inst.rs2 := 0.asUInt(5.W)