Add vadd example; riscv-pk patch; cp makefiles

patches/riscv-pk.patch

@@ -0,0 +1,19 @@
+diff --git a/machine/minit.c b/machine/minit.c
+index 5ad6d92..2185d4b 100644
+--- a/machine/minit.c
++++ b/machine/minit.c
+@@ -23,9 +23,11 @@ void* kernel_end;
+ 
+ static void mstatus_init()
+ {
+-  // Enable FPU
+-  if (supports_extension('D') || supports_extension('F'))
+-    write_csr(mstatus, MSTATUS_FS);
++  // Enable FPU and Custom Instruction
++  uintptr_t ms = 0;
++  ms = INSERT_FIELD(ms, MSTATUS_FS, 1);
++  ms = INSERT_FIELD(ms, MSTATUS_XS, 1);
++  write_csr(mstatus, ms);
+ 
+   // Enable user/supervisor use of perf counters
+   if (supports_extension('S'))

scripts/accel.json

@@ -0,0 +1,9 @@
+{
+  "RoCC":{
+    "custom0":{"pgm": "vadd", "func":"vadd"}
+  },
+  "TLL2":[
+    {"pgm":"vadd_tl", "func": "vadd", "addr":"0x20000"},
+    {"pgm":"", "func": "", "addr":""}
+  ]
+}

scripts/build_sbt_template

@@ -0,0 +1,187 @@
+import Tests._
+
+// This gives us a nicer handle  to the root project instead of using the
+// implicit one
+lazy val chipyardRoot = RootProject(file("."))
+
+lazy val commonSettings = Seq(
+  organization := "edu.berkeley.cs",
+  version := "1.0",
+  scalaVersion := "2.12.4",
+  traceLevel := 15,
+  test in assembly := {},
+  assemblyMergeStrategy in assembly := { _ match {
+    case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
+    case _ => MergeStrategy.first}},
+  scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
+  libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.5" % "test",
+  libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1",
+  libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+  libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0",
+  libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1",
+  libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10",
+  addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
+  unmanagedBase := (chipyardRoot / unmanagedBase).value,
+  allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"),
+  exportJars := true,
+  resolvers ++= Seq(
+    Resolver.sonatypeRepo("snapshots"),
+    Resolver.sonatypeRepo("releases"),
+    Resolver.mavenLocal))
+
+val rocketChipDir = file("generators/rocket-chip")
+
+lazy val firesimAsLibrary = sys.env.get("FIRESIM_STANDALONE") == None
+lazy val firesimDir = if (firesimAsLibrary) {
+  file("sims/firesim/sim/")
+} else {
+  file("../../")
+}
+
+// Checks for -DROCKET_USE_MAVEN.
+// If it's there, use a maven dependency.
+// Else, depend on subprojects in git submodules.
+def conditionalDependsOn(prj: Project): Project = {
+  if (sys.props.contains("ROCKET_USE_MAVEN")) {
+    prj.settings(Seq(
+      libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT",
+    ))
+  } else {
+    prj.dependsOn(testchipip)
+  }
+}
+
+/**
+  * It has been a struggle for us to override settings in subprojects.
+  * An example would be adding a dependency to rocketchip on midas's targetutils library,
+  * or replacing dsptools's maven dependency on chisel with the local chisel project.
+  *
+  * This function works around this by specifying the project's root at src/ and overriding
+  * scalaSource and resourceDirectory.
+  */
+def freshProject(name: String, dir: File): Project = {
+  Project(id = name, base = dir / "src")
+    .settings(
+      scalaSource in Compile := baseDirectory.value / "main" / "scala",
+      resourceDirectory in Compile := baseDirectory.value / "main" / "resources"
+    )
+}
+
+// Fork each scala test for now, to work around persistent mutable state
+// in Rocket-Chip based generators
+def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
+      val options = ForkOptions()
+      new Group(test.name, Seq(test), SubProcess(options))
+  } toSeq
+
+// Subproject definitions begin
+//
+// FIRRTL is handled as an unmanaged dependency. Make will build the firrtl jar
+// before launching sbt if any of the firrtl source files has been updated
+// The jar is dropped in chipyard's lib/ directory, which is used as the unmanagedBase
+// for all subprojects
+lazy val chisel  = (project in file("tools/chisel3"))
+
+lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter"))
+  .settings(commonSettings)
+
+lazy val treadle = (project in file("tools/treadle"))
+  .settings(commonSettings)
+
+lazy val chisel_testers = (project in file("tools/chisel-testers"))
+  .dependsOn(chisel, firrtl_interpreter, treadle)
+  .settings(
+      commonSettings,
+      libraryDependencies ++= Seq(
+        "junit" % "junit" % "4.12",
+        "org.scalatest" %% "scalatest" % "3.0.5",
+        "org.scalacheck" %% "scalacheck" % "1.14.0",
+        "com.github.scopt" %% "scopt" % "3.7.0"
+      )
+    )
+
+// Contains annotations & firrtl passes you may wish to use in rocket-chip without
+// introducing a circular dependency between RC and MIDAS
+lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
+
+ // Rocket-chip dependencies (subsumes making RC a RootProject)
+lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
+  .settings(commonSettings).dependsOn(midasTargetUtils)
+
+lazy val rocketMacros  = (project in rocketChipDir / "macros")
+  .settings(commonSettings)
+
+lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
+  .settings(commonSettings)
+  .dependsOn(chisel, hardfloat, rocketMacros)
+
+lazy val testchipip = (project in file("generators/testchipip"))
+  .dependsOn(rocketchip)
+  .settings(commonSettings)
+
+lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
+  .dependsOn(rocketchip, sifive_cache)
+  .settings(commonSettings)
+
+lazy val utilities = conditionalDependsOn(project in file("generators/utilities"))
+  .dependsOn(rocketchip, boom)
+  .settings(commonSettings)
+
+lazy val icenet = (project in file("generators/icenet"))
+  .dependsOn(rocketchip, testchipip)
+  .settings(commonSettings)
+
+lazy val hwacha = (project in file("generators/hwacha"))
+  .dependsOn(rocketchip)
+  .settings(commonSettings)
+
+lazy val boom = (project in file("generators/boom"))
+  .dependsOn(rocketchip)
+  .settings(commonSettings)
+
+lazy val sha3 = (project in file("generators/sha3"))
+  .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
+  .settings(commonSettings)
+
+lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
+  .dependsOn(chisel_testers, example)
+  .settings(commonSettings)
+
+lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/"))
+  .settings(commonSettings)
+
+lazy val barstoolsMacros = (project in file("./tools/barstools/macros/"))
+  .dependsOn(firrtl_interpreter, mdf, rocketchip)
+  .enablePlugins(sbtassembly.AssemblyPlugin)
+  .settings(commonSettings)
+
+lazy val dsptools = (project in file("./tools/dsptools"))
+  .dependsOn(chisel, chisel_testers)
+  .settings(
+      commonSettings,
+      libraryDependencies ++= Seq(
+        "org.typelevel" %% "spire" % "0.14.1",
+        "org.scalanlp" %% "breeze" % "0.13.2",
+        "junit" % "junit" % "4.12" % "test",
+        "org.scalatest" %% "scalatest" % "3.0.5" % "test",
+        "org.scalacheck" %% "scalacheck" % "1.14.0" % "test"
+  ))
+
+lazy val `rocket-dsptools` = (project in file("./tools/dsptools/rocket"))
+  .dependsOn(rocketchip, dsptools)
+  .settings(commonSettings)
+
+lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
+  .dependsOn(rocketchip)
+  .settings(commonSettings)
+
+lazy val sifive_cache = (project in file("generators/sifive-cache")).settings(
+    commonSettings,
+    scalaSource in Compile := baseDirectory.value / "craft"
+  ).dependsOn(rocketchip)
+
+// Library components of FireSim
+lazy val midas      = ProjectRef(firesimDir, "midas")
+lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
+
+

scripts/generate_accel.pl

@@ -48,10 +48,8 @@ sub generate_accel{
 
       system("mkdir -p $bm_path/src/main/c");
       chdir("$bm_path/src/main/c/") or die $!;
-      system("cp $RDIR/tools/centrifuge/examples/${PGM}/* $bm_path_c");
+      system("cp -H $RDIR/tools/centrifuge/examples/${PGM}/* $bm_path_c");
-      system("cp $RDIR/tools/centrifuge/scripts/run_hls.pl $bm_path_c");
+      system("cp -H $RDIR/tools/centrifuge/scripts/run_hls.pl $bm_path_c");
-      #system("cp $RDIR/hls/sw/time.h $bm_path/src/main/c/");
-      #system("cp $RDIR/hls/sw/rocc.h $bm_path/src/main/c/");
 
       # Specialize the Makefile for this function
       system("sed -i 's/^FUNC=.*/FUNC=$func/g' $bm_path_c/Makefile");
@@ -63,15 +61,15 @@ sub generate_accel{
       system("perl run_hls.pl ${PGM} ${FUNC} $prefix"); 
 
       if ($is_rocc) {
-          system("cp $RDIR/tools/centrifuge/scripts/run_chisel.pl $bm_path_c");
+          system("cp -H $RDIR/tools/centrifuge/scripts/run_chisel.pl $bm_path_c");
-          system("cp $RDIR/tools/centrifuge/scripts/generate_wrapper.pl $bm_path_c");
+          system("cp -H $RDIR/tools/centrifuge/scripts/generate_wrapper.pl $bm_path_c");
           system("perl run_chisel.pl ${PGM} ${FUNC} $prefix");
           system("perl generate_wrapper.pl ${PGM} ${FUNC} $idx_addr $prefix");
           #system("make clean");
           #system("make CUSTOM_INST=1");
       } else {
-          system("cp $RDIR/tools/centrifuge/scripts/run_chisel_tl.pl $bm_path_c");
+          system("cp -H $RDIR/tools/centrifuge/scripts/run_chisel_tl.pl $bm_path_c");
-          system("cp $RDIR/tools/centrifuge/scripts/generate_wrapper_tl.pl $bm_path_c");
+          system("cp -H $RDIR/tools/centrifuge/scripts/generate_wrapper_tl.pl $bm_path_c");
           system("perl run_chisel_tl.pl ${PGM} ${FUNC} $idx_addr $prefix");
           system("perl generate_wrapper_tl.pl ${PGM} ${FUNC} $idx_addr $prefix");
           #system("make clean");

scripts/generate_soc.pl

@@ -102,9 +102,13 @@ generate_config(\@RoCC_names, \@TLL2_names, $postfix);
 #print_xsim_cmd($postfix, 0);
 
 # Ax machines
-#compile_vcs("clean");
+compile_vcs("clean");
 #copy_verilog(\%hls_bm, "$rdir/sim/generated-src/f1/FireSimHLS-HLSFireSimRocketChipConfig-FireSimConfig/FPGATop.v");
 
+# SW
+# Copy Makefile Templates
+system("cp $scripts_dir/sw_aux/makefiles/* $rdir/generators/$soc_name/");
+
 sub print_xsim_cmd{
     my $postfix= $_[0];
     my $with_nic = $_[1];
@@ -150,7 +154,7 @@ sub compile_replace_rtl{
 sub compile_vcs{
     my $clean = $_[0];
     chdir("$rdir/sims/vcs");
-    system("make $clean debug CONFIG=");
+    system("make $clean CONFIG=HLSRocketConfig TOP=TopWithHLS debug -j16");
 }
 
 sub copy_verilog{
@@ -162,4 +166,3 @@ sub copy_verilog{
     }
 }
 
-

scripts/hls-setup.sh

@@ -0,0 +1,85 @@
+#!/bin/bash
+
+# Run this script on a fresh clone to initialize any patches or tweaks needed
+# This assumes you've already fully set up firesim normally (at least run build-setup.sh)
+
+# go to top-level dir
+pushd $(git rev-parse --show-toplevel)
+export RDIR=$(git rev-parse --show-toplevel)/../../
+
+# Set RDIR (path to top of firesim repo) globally since our scripts use it
+#sed -i 's/RDIR=/export RDIR=/' sourceme-f1-manager.sh
+#source sourceme-f1-manager.sh
+
+# modify the pk source code to enable pk for custom instructions
+pushd $RDIR/toolchains/riscv-tools/riscv-pk
+git apply $RDIR/tools/centrifuge/patches/riscv-pk.patch
+popd
+
+pushd $RDIR
+./scripts/build-toolchains.sh
+popd
+
+# modify the midas F1Transform to generate clock gating buffers for blackbox modules:
+# pushd $RDIR/sim/midas/src/main/scala/midas/passes
+# git apply $RDIR/hls/patches/Fame1Transform.scala.patch
+# popd
+
+# Patch Generator.scala and Rocketchip Fragmentator code for HLS
+# pushd $RDIR/sim/src/main/scala
+# git apply $RDIR/hls/patches/Generator.scala.patch 
+# cd $RDIR/sim/target-rtl/firechip/rocket-chip/src/main/scala
+# git apply $RDIR/hls/patches/Fragmenter.scala.patch
+# popd
+
+# Setup all the auxiliary makefiles for RISC-V baremetal compilation for print statement and etc.
+#cp $RDIR/tools/centrifuge/makefiles/* $RDIR/sim/target-rtl/firechip
+pushd $RDIR/tools/centrifuge/scripts/sw_aux/bm_linker_scripts
+make
+popd
+
+# Enable custom instruction and loadable kernel modules on riscv-linux
+#pushd $RDIR/sw/firesim-software/riscv-linux
+#touch arch/riscv/include/asm/module.h && touch arch/riscv/kernel/module-sections.c && touch arch/riscv/kernel/module.lds   
+#git apply $RDIR/hls/patches/riscv-linux.patch
+#popd
+#
+#pushd $CL_DIR/verif/scripts
+#git apply $RDIR/hls/patches/XSim_Makefile.patch 
+#touch top.vivado.vhd.f
+#popd
+#
+## Add Linux static memory allocator for the accelorator
+#cp $RDIR/hls/sw/riscv-linux/hls_mmap_static.c  $RDIR/sw/firesim-software/riscv-linux/mm/
+#echo "obj-y += hls_mmap_static.o" >> $RDIR/sw/firesim-software/riscv-linux/mm/Makefile
+#
+## Only on millennium machines:
+#if [ "$(domainname)" == "mill" ]; then
+#  # Enable VCS simluation with BUFGCE libraries.
+#  pushd $RDIR/sim/midas/src/main/cc
+#  git apply $RDIR/hls/patches/VCS_Makefile.patch
+#  popd
+#
+#  # Setup perl modules
+#  cpan JSON
+#  cpan Tie::File::AsHash
+#
+#  # Get vivado license stuff in the sourceme
+#  echo "
+#source /ecad/tools/fpga.bashrc
+#source /ecad/tools/xilinx/Vivado/2017.1/settings64.sh > /dev/null" >> $RDIR/sourceme-f1-manager.sh
+#fi
+#
+## Only on AWS FPGA AMI machines (see firesim/build-setup-nolog.sh for how this trick works):
+#if wget -T 1 -t 3 -O /dev/null http://169.254.169.254/; then
+#  # # Update Makefiles for Xsim to support VHDL simluation.
+#  pushd $CL_DIR/verif/scripts
+#  git apply $RDIR/hls/patches/XSim_Makefile.patch 
+#  touch top.vivado.vhd.f
+#  popd
+
+  # Setup perl modules
+#  sudo yum install -y cpan
+#  sudo cpan JSON
+#  sudo yum install -y perl-Tie-IxHash
+#fi