431 lines
20 KiB
Scala
431 lines
20 KiB
Scala
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package memControl
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import Chisel._
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import Chisel.ImplicitConversions._
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import freechips.rocketchip.tile._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.rocket._
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import freechips.rocketchip.tilelink._
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//import freechips.rocketchip.util.InOrderArbiter
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import freechips.rocketchip.util._
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import freechips.rocketchip.system._
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import vivadoHLS._
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import controlUtils._
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class RequestParserIO(dataWidth: Int, addrWidth: Int) extends Bundle{
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val reqIn = new ApBusReq(dataWidth, addrWidth).flip
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val reqOut = new ApBusReq(dataWidth, addrWidth)
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val offsetAddr = UInt(INPUT, width=addrWidth)
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val loadOffset = Bool(INPUT)
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override def cloneType: this.type = new RequestParserIO(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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class RequestParser(dataWidth: Int, addrWidth: Int) extends Module{
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val io = IO(new RequestParserIO(dataWidth, addrWidth))
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val offsetReg = Reg(init = UInt(0, width=addrWidth))
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val multAmt = UInt(dataWidth/8)
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when(io.loadOffset){
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offsetReg := io.offsetAddr
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}
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io.reqOut.din := io.reqIn.din
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io.reqOut.dataout := io.reqIn.dataout
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io.reqOut.size := io.reqIn.size
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io.reqOut.address := (io.reqIn.address*multAmt) + offsetReg
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}
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class TimestampedRequestIO(dataWidth:Int, addrWidth:Int, counterSize: Int) extends Bundle{
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val req = new ApBusReq(dataWidth, addrWidth)
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val timestamp = UInt(INPUT, log2Up(counterSize))
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override def cloneType: this.type = new TimestampedRequestIO(dataWidth, addrWidth, counterSize).asInstanceOf[this.type]
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}
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class ApBusReqType (dataWidth:Int, addrWidth:Int) extends Bundle{
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//Req specific lines
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//Specifies a write request
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val din = Bool() //req_din in verilog
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//Lines used for req
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val address = UInt(width = addrWidth)
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val dataout = UInt(width = dataWidth)
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val size = UInt(width = addrWidth)
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override def cloneType: this.type = new ApBusReqType(dataWidth, addrWidth).asInstanceOf[this.type]
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}
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class TimestampedRequestIOType(dataWidth:Int, addrWidth:Int, counterSize: Int) extends Bundle{
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val req = new ApBusReqType(dataWidth, addrWidth)
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val timestamp = UInt(width = log2Up(counterSize))
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override def cloneType: this.type = new TimestampedRequestIOType(dataWidth, addrWidth, counterSize).asInstanceOf[this.type]
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}
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class RequestIngestIO(dataWidth: Seq[Int], addrWidth: Seq[Int], counterSize: Int, inputBufferLen: Int) extends Bundle{
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//val reqsIn = Vec.tabulate(dataWidth.length)((i) => Wire(new ApBusReq(dataWidth(i), addrWidth(i)).flip))
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val reqsIn = HeterogeneousBag(dataWidth.zip(addrWidth).map {
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case (dw, aw) => new ApBusReq(dw, aw)
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}).flip
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val reqsFullN = Vec(dataWidth.length, Output(Bool()))
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//val reqsWrite = Vec(dataWidth.length, Bool(INPUT)).flip
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val reqsWrite = Vec(dataWidth.length, Input(Bool()))
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//val offsetAddrs = Vec.tabulate(dataWidth.length)((i) => UInt(INPUT, width=addrWidth(i)))
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//val offsetAddrs = HeterogeneousBag(addrWidth.map(aw => UInt(INPUT, width = aw)))
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val offsetAddrs = HeterogeneousBag(addrWidth.map(aw => Input(UInt(aw.W))))
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//val loadOffsets = Vec(dataWidth.length, Bool(INPUT)).flip
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val loadOffsets = Vec(dataWidth.length, Input(Bool()))
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val newRequests = UInt(OUTPUT, width = log2Up(dataWidth.length)+1) //The number of new requests recieved in this cycle (used to track number of outstanding requests)
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//The widths are the maximums of all of the input widths
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val reqOut = Decoupled(new ApBusReq(if (dataWidth.length > 0) dataWidth.max else 0, if (addrWidth.length > 0) addrWidth.max else 0))
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val selectedBus = UInt(OUTPUT, log2Up(dataWidth.length))
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override def cloneType: this.type = new RequestIngestIO(dataWidth, addrWidth, counterSize, inputBufferLen).asInstanceOf[this.type]
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}
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class RequestIngest(dataWidth: Seq[Int], addrWidth: Seq[Int], inputBufferLen: Int) extends Module{
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val busCount = dataWidth.length
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//We only need enough counter values to account for the worst case scenario when memory is stalled and each buffer is filled one at a time
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//Adding an extra 1 is probably overly conservative as the extra one may be reassigned but is not at the front of the queue. If it was, then a queue is not
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//Taking the base 2 log and rasing 2 to that power ensures that the overflow semantics are what is expected. This is important for the priority difference
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val counterSize = BigInt(2).pow(log2Up(inputBufferLen*busCount)).toInt
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val io = IO(new RequestIngestIO(dataWidth, addrWidth, counterSize, inputBufferLen))
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val counter = Counter(counterSize)
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val prevTimestamp = Reg(init = UInt(0, width=log2Up(counterSize)))
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val parsers = Seq.tabulate(busCount)((i) => Module(new RequestParser(dataWidth(i), addrWidth(i))).io)
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//val queues = Vec.tabulate(busCount)((i) => Module(new Queue(new TimestampedRequestIOType(dataWidth(i), addrWidth(i), log2Up(counterSize)), inputBufferLen)))
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val queues = Seq.tabulate(busCount)((i) => Module(new Queue(new TimestampedRequestIOType(dataWidth(i), addrWidth(i), log2Up(counterSize)), inputBufferLen)).io)
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/*val queues = HeterogeneousBag(dataWidth.zip(addrWidth).map{
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case (dw, aw) => Module(new Queue(new TimestampedRequestIOType(dw, aw, log2Up(counterSize)), inputBufferLen))
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})*/
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//Vec.tabulate(busCount)((i) => Module(new Queue(new TimestampedRequestIO(dataWidth(i), addrWidth(i), log2Up(counterSize)), inputBufferLen)).io)
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val arbiter = Module(new PriorityArbiter(new ApBusReq(if (dataWidth.length > 0) dataWidth.max else 0, if (addrWidth.length > 0) addrWidth.max else 0), busCount, log2Up(counterSize)))
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val incrCounter = Wire(Bool(false))
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if (dataWidth.length > 0) {
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incrCounter := io.reqsWrite.reduce(_||_)
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}
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//+1 is because we need to be able to represent 0 and BusCount not BusCount-1
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val requestsUInt = io.reqsWrite.map((x) => Mux(x, UInt(1, width=busCount), UInt(0, width=busCount+1)))
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if (dataWidth.length > 0) {
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io.newRequests := requestsUInt.reduce(_+_)
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}
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//Increment counter when any request comes in
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when(incrCounter){
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counter.inc()
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}
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for(i <- 0 until busCount){
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parsers(i).offsetAddr := io.offsetAddrs(i)
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parsers(i).loadOffset := io.loadOffsets(i)
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parsers(i).reqIn := io.reqsIn(i)
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//parsers(i).reqIn <> io.reqsIn(i)
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queues(i).enq.bits.req := parsers(i).reqOut
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queues(i).enq.bits.timestamp := counter.value //put in the timestamp!
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io.reqsFullN(i) := queues(i).enq.ready
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queues(i).enq.valid := io.reqsWrite(i)
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queues(i).deq.ready := arbiter.io.in(i).ready
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arbiter.io.in(i).valid := queues(i).deq.valid
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arbiter.io.in(i).bits := queues(i).deq.bits.req
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//Priority is oldest first. It is defined as the difference from the last serviced timestamp
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arbiter.io.priority(i) := queues(i).deq.bits.timestamp - prevTimestamp //This works even with overlfow so long as counterSize is a power of 2
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}
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when(arbiter.io.out.valid && io.reqOut.ready){
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prevTimestamp := prevTimestamp + arbiter.io.priorityOut
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}
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//io.reqOut := arbiter.io.out
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io.reqOut.valid := arbiter.io.out.valid
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arbiter.io.out.ready := io.reqOut.ready
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io.reqOut.bits := arbiter.io.out.bits
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io.selectedBus := arbiter.io.chosen
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}
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class RequestIssuerIO(dataWidth: Int, addrWidth:Int, maxReqWidth:Int, numBus:Int, roccAddrWidth:Int, roccDataWidth:Int, roccTagWidth:Int, roccCmdWidth:Int, roccTypWidth:Int) extends Bundle{
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//Incoming request from arbiter
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//val reqIn = Decoupled(new ApBusReq(dataWidth, addrWidth)).flip
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val reqIn = Flipped(Decoupled(new ApBusReq(dataWidth, addrWidth)))
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//The bus that the request came from
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val reqBus = UInt(INPUT, width=log2Up(numBus))
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//Lines for table address check and for updating the table
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val accessWidth = UInt(OUTPUT, width=maxReqWidth)
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val accessRead = Bool(INPUT)
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val conflict = Bool(INPUT)
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//val tagQueueIO = Decoupled(UInt(OUTPUT, width=roccTagWidth)).flip
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val tagQueueIO = Flipped(Decoupled(Output(UInt(roccTagWidth.W))))
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val busNum = UInt(OUTPUT, width=log2Up(numBus))
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//RoCC Lines
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val roCCReqAddr = UInt(OUTPUT, width = roccAddrWidth) // coreMaxAddrBits)
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val roCCReqTag = UInt(OUTPUT, width = roccTagWidth) //coreDCacheReqTagBits)
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val roCCReqCmd = UInt(OUTPUT, width = roccCmdWidth) //M_SZ)
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val roCCReqTyp = UInt(OUTPUT, width = roccTypWidth) //
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val roCCReqData = UInt(OUTPUT, width = roccDataWidth) //coreDataBits)
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val roCCReqValid = Bool(OUTPUT)
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val roCCReqRdy = Bool(INPUT)
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val reqWidth = UInt(OUTPUT, width = maxReqWidth) //Pass to table to specify width of request
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val reqSent = Bool(OUTPUT)
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override def cloneType: this.type = new RequestIssuerIO(dataWidth, addrWidth, maxReqWidth, numBus, roccAddrWidth, roccDataWidth, roccTagWidth, roccCmdWidth, roccTypWidth).asInstanceOf[this.type]
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}
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//maxReqBytes = 8 (64 bit) in our case
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class RequestIssuer(dataWidth: Int, addrWidth:Int, maxReqBytes:Int, roccAddrWidth:Int, roccDataWidth:Int, roccTagWidth:Int, roccCmdWidth:Int, roccTypWidth:Int, busDataWidths:Seq[Int]) extends Module{
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val maxReqWidth = log2Up(maxReqBytes)
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val numBus = busDataWidths.length
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val io = IO(new RequestIssuerIO(dataWidth, addrWidth, maxReqWidth, numBus, roccAddrWidth, roccDataWidth, roccTagWidth, roccCmdWidth, roccTypWidth))
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if (busDataWidths.length > 0) {
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val busByteWidth = Vec(busDataWidths.map((x) => UInt(x)/UInt(8)))
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val currentByteWidth = busByteWidth(io.reqBus)
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io.busNum := io.reqBus
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io.roCCReqAddr := io.reqIn.bits.address
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io.roCCReqData := io.reqIn.bits.dataout
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io.roCCReqTag := io.tagQueueIO.bits
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io.roCCReqCmd := Mux(io.reqIn.bits.din, M_XWR, M_XRD) //Set the transaction type (Write / Read)
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io.roCCReqTyp := Mux(currentByteWidth===UInt(8), log2Ceil(8).U, Mux(currentByteWidth===UInt(4), log2Ceil(4).U, Mux(currentByteWidth===UInt(2), log2Ceil(2).U, log2Ceil(1).U))) //Set transaction width
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io.reqWidth := currentByteWidth
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io.accessWidth := currentByteWidth
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io.roCCReqValid := io.reqIn.valid && !io.conflict && io.tagQueueIO.valid
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val memTransactSent = io.reqIn.valid && io.roCCReqRdy && !io.conflict && io.tagQueueIO.valid
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io.reqIn.ready := memTransactSent
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io.tagQueueIO.ready := memTransactSent //We used a tag when we issued a request
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io.reqSent := memTransactSent
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}
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}
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class RoutingTableIO(tagWidth:Int, numBus:Int, addrWidth: Int, maxReqWidth: Int) extends Bundle{
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val reqValid = Bool(INPUT)
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val reqTag = UInt(INPUT, width = tagWidth)
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val reqWrite = Bool(INPUT) //If the transaction is a write
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val reqAddr = UInt(INPUT, width = addrWidth)
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val reqBus = UInt(INPUT, log2Up(numBus))
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val reqWidth = UInt(INPUT, width = maxReqWidth)
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val checkAddr = UInt(INPUT, width = addrWidth)
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val checkWidth = UInt(INPUT, width = maxReqWidth)
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val checkRead = Bool(INPUT)
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val conflict = Bool(OUTPUT)
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val respTag = UInt(INPUT, width = tagWidth)
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val respVaid = Bool(INPUT)
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val respBus = UInt(OUTPUT, width = log2Up(numBus))
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override def cloneType: this.type = new RoutingTableIO(tagWidth, numBus, addrWidth, maxReqWidth).asInstanceOf[this.type]
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}
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//maxReqBytes = 8 (64 bit) in our case
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class RoutingTable(tagWidth:Int, numTags:Int, numBus:Int, addrWidth: Int, maxReqBytes: Int) extends Module{
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val maxReqWidth = log2Up(maxReqBytes)
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//val numTags = BigInt(2).pow(tagWidth).toInt
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val io = IO(new RoutingTableIO(tagWidth, numBus, addrWidth, maxReqWidth))
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if (addrWidth > 0) {
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val v = Reg(Vec.fill(numTags)(Bool(false))) //valid (outstanding memory request)
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val write = Reg(Vec.fill(numTags)(Bool(false))) //outstanding request is a write
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val addr = Reg(Vec.fill(numTags)(UInt(0, width=addrWidth)))
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val width = Reg(Vec.fill(numTags)(UInt(0, width=maxReqWidth)))
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val bus = Reg(Vec.fill(numTags)(UInt(0, width=log2Up(numBus))))
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//write Req into table
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when(io.reqValid){
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v(io.reqTag) := Bool(true) //Set table entry as valid
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write(io.reqTag) := io.reqWrite //Set write flag
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addr(io.reqTag) := io.reqAddr //Set addr
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width(io.reqTag) := io.reqWidth //Set transaction width (in bytes)
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bus(io.reqTag) := io.reqBus //Set the requesting bus
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}
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//clear returned transaction. The tag queue prevents accedently claring a tag that has not yet returned
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when(io.respVaid){
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v(io.respTag) := Bool(false) //This entry is no longer valid
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}
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//Return the bus that requsted the returning transaction
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io.respBus := bus(io.respTag)
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//Reads can execute if there is no outstanding write to the address (v==false || write==false)
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// Reads stall when v==true and write==true
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//Writes can only occure if there are no outstanding ops (v==false)
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// Writes stall when v==true
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val addrsConflicting = Vec.tabulate(numTags)((i) => !((io.checkAddr + io.checkWidth <= addr(i)) || (addr(i) + width(i) <= io.checkAddr)))
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//There is a conflict if: the address is conflicting, the entry is valid, and if(reading, there is an outstanding write)
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val conflicting = Vec.tabulate(numTags)((i) => addrsConflicting(i) && v(i) && Mux(io.checkRead, write(i), Bool(true)))
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io.conflict := conflicting.reduce(_||_)
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}
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}
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class MemControllerIO(dataWidth:Seq[Int], addrWidth:Seq[Int], roccAddrWidth:Int, roccDataWidth:Int, roccTagWidth:Int, roccCmdWidth:Int, roccTypWidth:Int) extends Bundle{
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//----ap_bus requests----
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val reqsIn = HeterogeneousBag(dataWidth.zip(addrWidth).map {
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case (dw, aw) => new ApBusReq(dw, aw)
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}).flip
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//Decoupled signals for requests
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val reqsFullN = Vec(dataWidth.length, Bool(OUTPUT))
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//val reqsWrite = Vec(dataWidth.length, Bool(INPUT)).flip
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val reqsWrite = Vec(dataWidth.length, Input(Bool()))
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//Offset address lines
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//val offsetAddrs = Vec.tabulate(dataWidth.length)((i) => UInt(INPUT, width=addrWidth(i)))
|
||
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|
val offsetAddrs = HeterogeneousBag(addrWidth.map(aw => UInt(INPUT, width = aw)))
|
||
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|
//val loadOffsets = Vec(dataWidth.length, Bool(INPUT)).flip
|
||
|
|
val loadOffsets = Vec(dataWidth.length,Input(Bool()))
|
||
|
|
|
||
|
|
//----status line----
|
||
|
|
val memBusy = Bool(OUTPUT)
|
||
|
|
|
||
|
|
//----ap_bus response----
|
||
|
|
//val rspOut = Vec.tabulate(dataWidth.length)((i) => new ApBusRsp(dataWidth(i)).flip)
|
||
|
|
val rspOut = HeterogeneousBag(dataWidth.map(dw => new ApBusRsp(dw))).flip
|
||
|
|
val rsp_empty_n = Vec(dataWidth.length, Output(Bool())) //This is the same as valid
|
||
|
|
val rsp_read = Vec(dataWidth.length, Input(Bool())) //This is the same as ready
|
||
|
|
|
||
|
|
//----RoCC Mem Req----
|
||
|
|
val roCCReqAddr = UInt(OUTPUT, width = roccAddrWidth) // coreMaxAddrBits)
|
||
|
|
val roCCReqTag = UInt(OUTPUT, width = roccTagWidth) //coreDCacheReqTagBits)
|
||
|
|
val roCCReqCmd = UInt(OUTPUT, width = roccCmdWidth) //M_SZ)
|
||
|
|
val roCCReqTyp = UInt(OUTPUT, width = roccTypWidth) //MT_SZ)
|
||
|
|
val roCCReqData = UInt(OUTPUT, width = roccDataWidth) //
|
||
|
|
val roCCReqValid = Bool(OUTPUT)
|
||
|
|
val roCCReqRdy = Bool(INPUT)
|
||
|
|
|
||
|
|
//val roCCRespAddr = UInt(INPUT, width = roccAddrWidth) // coreMaxAddrBits)
|
||
|
|
val roCCRspTag = UInt(INPUT, width = roccTagWidth) //coreDCacheReqTagBits)
|
||
|
|
val roCCRspCmd = UInt(INPUT, width = roccCmdWidth) //M_SZ)
|
||
|
|
val roCCRspData = UInt(INPUT, width = roccDataWidth) //MT_SZ)
|
||
|
|
//val roCCRespTyp = UInt(INPUT, width = roccTypWidth) //MT_SZ)
|
||
|
|
val roCCRspValid = Bool(INPUT)
|
||
|
|
override def cloneType: this.type = new MemControllerIO(dataWidth, addrWidth, roccAddrWidth, roccDataWidth, roccTagWidth, roccCmdWidth, roccTypWidth).asInstanceOf[this.type]
|
||
|
|
}
|
||
|
|
|
||
|
|
class MemController(dataWidth:Seq[Int], addrWidth:Seq[Int], reqBufferLen:Int, rspBufferLen:Int, maxReqBytes:Int, roccAddrWidth:Int, roccDataWidth:Int, roccTagWidth:Int, roccCmdWidth:Int, roccTypWidth:Int, numTags:Int, tagOffset:Int ) extends Module{
|
||
|
|
val io = IO(new MemControllerIO(dataWidth, addrWidth, roccAddrWidth, roccDataWidth, roccTagWidth, roccCmdWidth, roccTypWidth))
|
||
|
|
|
||
|
|
val numBus = dataWidth.length
|
||
|
|
if (numBus > 0){
|
||
|
|
val reqIngest = Module(new RequestIngest(dataWidth, addrWidth, reqBufferLen))
|
||
|
|
val reqIssuer = Module(new RequestIssuer(if (dataWidth.length > 0) dataWidth.max else 0, if (addrWidth.length > 0) addrWidth.max else 0, maxReqBytes, roccAddrWidth, roccDataWidth, roccTagWidth, roccCmdWidth, roccTypWidth, dataWidth))
|
||
|
|
val scoreboard = Module(new RoutingTable(roccTagWidth, numTags, numBus, if (addrWidth.length > 0) addrWidth.max else 0, maxReqBytes))
|
||
|
|
|
||
|
|
//Tags may have an offset if this is not the only accelerator in the system
|
||
|
|
val tags = (tagOffset until (tagOffset+numTags))
|
||
|
|
val tagUInts = tags.map((x) => UInt(x, width=roccTagWidth).asUInt)
|
||
|
|
val tagQueue = Module(new RegisterQueue(gen=UInt(width=roccTagWidth), entries=numTags, initVals=tagUInts, flow=true))
|
||
|
|
val rspQueues = Seq.tabulate(numBus)((i) => Module(new Queue(UInt(width=dataWidth(i)), rspBufferLen)).io)
|
||
|
|
val validDemux = Module(new ValidDemux(numBus))
|
||
|
|
|
||
|
|
val currentRequestNum = Reg(init=UInt(0, width=(reqBufferLen*numBus+1+numTags)))
|
||
|
|
|
||
|
|
//Logic for number of outstanding requests
|
||
|
|
currentRequestNum := currentRequestNum + reqIngest.io.newRequests - Mux(io.roCCRspValid, UInt(1), UInt(0))
|
||
|
|
io.memBusy := currentRequestNum =/= UInt(0)
|
||
|
|
|
||
|
|
//==== Ingest Logic ====
|
||
|
|
//Hook up ap_bus request lines to ingest logic
|
||
|
|
//reqIngest.io.reqsIn <> io.reqsIn
|
||
|
|
reqIngest.io.reqsIn := io.reqsIn
|
||
|
|
io.reqsFullN := reqIngest.io.reqsFullN
|
||
|
|
reqIngest.io.reqsWrite := io.reqsWrite
|
||
|
|
//reqIngest.io.offsetAddrs := io.offsetAddrs
|
||
|
|
io.offsetAddrs := reqIngest.io.offsetAddrs
|
||
|
|
reqIngest.io.loadOffsets := io.loadOffsets
|
||
|
|
|
||
|
|
//val newRequests
|
||
|
|
|
||
|
|
//val reqOut
|
||
|
|
//val selectedBus
|
||
|
|
|
||
|
|
//====Req Issuer ====
|
||
|
|
//Incoming request from arbiter
|
||
|
|
//reqIssuer.io.reqIn <> reqIngest.io.reqOut
|
||
|
|
reqIssuer.io.reqIn.bits := reqIngest.io.reqOut.bits
|
||
|
|
reqIssuer.io.reqIn.valid := reqIngest.io.reqOut.valid
|
||
|
|
reqIngest.io.reqOut.ready := reqIssuer.io.reqIn.ready
|
||
|
|
//The bus that the request came from
|
||
|
|
reqIssuer.io.reqBus := reqIngest.io.selectedBus
|
||
|
|
|
||
|
|
//Lines for table address check and for updating the table
|
||
|
|
//val accessWidth
|
||
|
|
//val containsAddr
|
||
|
|
//reqIssuer.io.tagQueue <> tagQueue.io.deq
|
||
|
|
reqIssuer.io.tagQueueIO.bits := tagQueue.io.deq.bits
|
||
|
|
reqIssuer.io.tagQueueIO.valid := tagQueue.io.deq.valid
|
||
|
|
tagQueue.io.deq.ready := reqIssuer.io.tagQueueIO.ready
|
||
|
|
//val busNum
|
||
|
|
//val reqWidth //Pass to table to specify width of request
|
||
|
|
|
||
|
|
//RoCC Lines
|
||
|
|
io.roCCReqAddr := reqIssuer.io.roCCReqAddr
|
||
|
|
io.roCCReqTag := reqIssuer.io.roCCReqTag
|
||
|
|
io.roCCReqCmd := reqIssuer.io.roCCReqCmd
|
||
|
|
io.roCCReqTyp := reqIssuer.io.roCCReqTyp
|
||
|
|
io.roCCReqValid := reqIssuer.io.roCCReqValid
|
||
|
|
reqIssuer.io.roCCReqRdy := io.roCCReqRdy
|
||
|
|
io.roCCReqData := reqIssuer.io.roCCReqData
|
||
|
|
|
||
|
|
//====Scoreboard====
|
||
|
|
scoreboard.io.reqValid := reqIssuer.io.reqSent //Do not commit into the table unles there is a fire
|
||
|
|
scoreboard.io.reqTag := reqIssuer.io.roCCReqTag
|
||
|
|
scoreboard.io.reqWrite := (reqIssuer.io.roCCReqCmd === M_XWR) //If the transaction is a write
|
||
|
|
scoreboard.io.reqAddr := reqIssuer.io.roCCReqAddr
|
||
|
|
scoreboard.io.reqBus := reqIssuer.io.busNum
|
||
|
|
scoreboard.io.reqWidth := reqIssuer.io.reqWidth
|
||
|
|
|
||
|
|
scoreboard.io.checkAddr := reqIssuer.io.roCCReqAddr
|
||
|
|
scoreboard.io.checkWidth := reqIssuer.io.accessWidth
|
||
|
|
scoreboard.io.checkRead := reqIssuer.io.accessRead
|
||
|
|
reqIssuer.io.conflict := scoreboard.io.conflict
|
||
|
|
|
||
|
|
scoreboard.io.respTag := io.roCCRspTag
|
||
|
|
scoreboard.io.respVaid := io.roCCRspValid
|
||
|
|
//val scoreboard.io.respBus
|
||
|
|
|
||
|
|
//====TagQueue====
|
||
|
|
tagQueue.io.enq.bits := io.roCCRspTag
|
||
|
|
tagQueue.io.enq.valid := io.roCCRspValid
|
||
|
|
|
||
|
|
//====Demux=====
|
||
|
|
validDemux.io.validIn := io.roCCRspValid && io.roCCRspCmd===M_XRD //Only return to the bus if this is a response to a read request
|
||
|
|
validDemux.io.validSelect := scoreboard.io.respBus
|
||
|
|
//val validOut = Vec.fill(fanout)(Bool(OUTPUT))
|
||
|
|
|
||
|
|
//====RespQueues====
|
||
|
|
for(i <- 0 until numBus){
|
||
|
|
rspQueues(i).enq.bits := io.roCCRspData((dataWidth(i)-1),0) //Pass the data to all output queues (slicing to approprite width), only give one the valid signal
|
||
|
|
rspQueues(i).enq.valid := validDemux.io.validOut(i)
|
||
|
|
io.rspOut(i).datain := rspQueues(i).deq.bits
|
||
|
|
io.rsp_empty_n(i) := rspQueues(i).deq.valid
|
||
|
|
rspQueues(i).deq.ready := io.rsp_read(i)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|