55 lines
2.6 KiB
MLIR
55 lines
2.6 KiB
MLIR
// RUN: scalehls-opt -scalehls-simplify-affine-if %s | FileCheck %s
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#map = affine_map<(d0) -> (d0 + 1)>
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#set0 = affine_set<(d0, d1) : (d0 - d1 >= 0)>
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#set1 = affine_set<(d0) : (d0 == 0)>
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module {
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func @test_syrk(%arg0: f32, %arg1: f32, %arg2: memref<16x16xf32, 1>, %arg3: memref<16x16xf32, 1>) attributes {func_directive = #hls.fd<pipeline=false, targetInterval=1, dataflow=false>, top_func} {
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affine.for %arg4 = 0 to 16 step 2 {
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affine.for %arg5 = 0 to 16 {
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affine.for %arg6 = 0 to 16 {
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// CHECK: affine.if #set0(%arg5, %arg6) {
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affine.if #set0(%arg5, %arg6) {
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// CHECK: %1 = affine.load %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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%1 = affine.load %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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%2 = arith.mulf %arg1, %1 : f32
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affine.if #set1(%arg4) {
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affine.store %2, %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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}
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%3 = affine.load %arg2[%arg5, %arg4] : memref<16x16xf32, 1>
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%4 = affine.load %arg2[%arg6, %arg4] : memref<16x16xf32, 1>
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%5 = affine.load %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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%6 = arith.mulf %arg0, %3 : f32
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%7 = arith.mulf %6, %4 : f32
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%8 = arith.addf %7, %5 : f32
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affine.store %8, %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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}
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// CHECK-NOT: %0 = affine.apply #map(%arg4)
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// CHECK-NOT: affine.if #set0(%arg5, %arg6) {
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%0 = affine.apply #map(%arg4)
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affine.if #set0(%arg5, %arg6) {
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// CHECK-NOT: %1 = affine.load %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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// CHECK: %9 = affine.load %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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%1 = affine.load %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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%2 = arith.mulf %arg1, %1 : f32
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affine.if #set1(%0) {
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affine.store %2, %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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}
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%3 = affine.load %arg2[%arg5, %arg4 + 1] : memref<16x16xf32, 1>
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%4 = affine.load %arg2[%arg6, %arg4 + 1] : memref<16x16xf32, 1>
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%5 = affine.load %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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%6 = arith.mulf %arg0, %3 : f32
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%7 = arith.mulf %6, %4 : f32
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%8 = arith.addf %7, %5 : f32
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affine.store %8, %arg3[%arg5, %arg6] : memref<16x16xf32, 1>
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}
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} {loop_directive = #hls.ld<pipeline=true, targetII=2, dataflow=false, flatten=false>, parallel}
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} {loop_directive = #hls.ld<pipeline=false, targetII=1, dataflow=false, flatten=true>, parallel}
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} {loop_directive = #hls.ld<pipeline=false, targetII=1, dataflow=false, flatten=true>}
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return
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}
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}
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