27 lines
1.4 KiB
MLIR
27 lines
1.4 KiB
MLIR
// RUN: scalehls-translate -emit-hlscpp %s | FileCheck %s
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func @callee(%arg0: index, %arg1: memref<16xindex>) -> (index, index, memref<16xindex>, memref<16xindex>) attributes {func_directive = #hls.fd<pipeline=false, targetInterval=1, dataflow=false>} {
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// CHECK-NOT: #pragma HLS interface s_axilite port=return bundle=ctrl
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// CHECK-NOT: #pragma HLS interface s_axilite port=v0 bundle=ctrl
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// CHECK-NOT: #pragma HLS interface s_axilite port=v2 bundle=ctrl
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// CHECK-NOT: #pragma HLS interface s_axilite port=v3 bundle=ctrl
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%0 = affine.load %arg1[%arg0] : memref<16xindex>
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%1 = affine.load %arg1[%arg0 + 1] : memref<16xindex>
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%2 = memref.alloc() : memref<16xindex>
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%3 = memref.alloc() : memref<16xindex>
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return %0, %1, %2, %3 : index, index, memref<16xindex>, memref<16xindex>
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}
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func @test_call(%arg0: index, %arg1: memref<16xindex>) -> (index, memref<16xindex>) attributes {func_directive = #hls.fd<pipeline=false, targetInterval=1, dataflow=false>, top_func} {
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// CHECK: #pragma HLS interface s_axilite port=return bundle=ctrl
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// CHECK: #pragma HLS interface s_axilite port=v6 bundle=ctrl
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// CHECK: #pragma HLS interface s_axilite port=v8 bundle=ctrl
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// CHECK: int v10;
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// CHECK: int v11[16];
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// CHECK: callee(v6, v7, &*v8, &v10, v9, v11);
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%0:4 = call @callee(%arg0, %arg1) : (index, memref<16xindex>) -> (index, index, memref<16xindex>, memref<16xindex>)
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return %0#0, %0#2 : index, memref<16xindex>
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}
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