63 lines
1.7 KiB
C++
63 lines
1.7 KiB
C++
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//===------------------------------------------------------------*- C++ -*-===//
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//
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// Automatically generated file for High-level Synthesis (HLS).
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//
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//===----------------------------------------------------------------------===//
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#include <algorithm>
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#include <ap_axi_sdata.h>
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#include <ap_fixed.h>
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#include <ap_int.h>
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#include <hls_math.h>
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#include <hls_stream.h>
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#include <math.h>
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#include <stdint.h>
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using namespace std;
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/// This is top function.
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/// Latency=201334786
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/// DSP=10
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void bicg_4096(
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float v0[4096][4096],
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float v1[4096],
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float v2[4096],
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float v3[4096],
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float v4[4096]
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) { // L2
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#pragma HLS interface s_axilite port=return bundle=ctrl
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#pragma HLS interface bram port=v0
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#pragma HLS interface bram port=v1
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#pragma HLS interface bram port=v2
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#pragma HLS interface bram port=v3
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#pragma HLS interface bram port=v4
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#pragma HLS resource variable=v0 core=ram_s2p_bram
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#pragma HLS resource variable=v1 core=ram_s2p_bram
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#pragma HLS resource variable=v2 core=ram_s2p_bram
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#pragma HLS resource variable=v3 core=ram_s2p_bram
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#pragma HLS resource variable=v4 core=ram_s2p_bram
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for (int v5 = 0; v5 < 4096; v5 += 1) { // L3, S[0,201334786), latency=49154
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for (int v6 = 0; v6 < 4096; v6 += 1) { // L4, S[0,49154), latency=12
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float v7 = v1[v6]; // L5, S[4,6)
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float v8 = v4[v5]; // L6, S[0,2)
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float v9 = v0[v5][v6]; // L7, S[0,2)
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float v10 = v8 * v9; // L8, S[2,6)
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float v11 = v7 + v10; // L9, S[6,11)
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v1[v6] = v11; // L10, S[11,12)
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float v12 = v2[v5]; // L11, S[4,6)
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float v13 = v3[v6]; // L12, S[0,2)
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float v14 = v9 * v13; // L13, S[2,6)
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float v15 = v12 + v14; // L14, S[6,11)
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v2[v5] = v15; // L15, S[11,12)
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}
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}
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}
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