Remove config folder; Update -multiple-level-dse to -dse

This commit is contained in:
Hanchen Ye 2021-09-30 04:57:45 -05:00
parent 2d42d2d6b9
commit ddf17f2ae8
4 changed files with 3 additions and 70 deletions

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@ -7,7 +7,7 @@ Please check out our [arXiv paper](https://arxiv.org/abs/2107.11673) for more de
## Quick Start
### 1. Download and Install ScaleHLS
To build ScaleHLS, run:
To build ScaleHLS with HLS C front-end, run:
```sh
$ git clone --recursive git@github.com:hanchenye/scalehls.git
$ mkdir scalehls/build
@ -37,7 +37,7 @@ $ cd scalehls
$ # HLS C programs parsing and automatic kernel-level design space exploration.
$ mlir-clang samples/polybench/gemm/gemm_32.c -function=gemm_32 -memref-fullrank -S | \
scalehls-opt -multiple-level-dse="top-func=gemm_32 output-path=./ target-spec=config/target-spec.ini" \
scalehls-opt -dse="top-func=gemm_32 output-path=./ target-spec=samples/polybench/target-spec.ini" \
-debug-only=scalehls > /dev/null
$ scalehls-translate -emit-hlscpp gemm_32_pareto_0.mlir > gemm_32_pareto_0.cpp

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@ -1,26 +0,0 @@
[config]
# input and output information
inputChannel=3
inputHeight=32
inputWidth=32
outputChannel=10
# Generation rules
batchSize=1
minChannel=8
maxChannel=64
poolingNumber=3
# Bypass information
bypassNumber=1
minBypassLength=2
maxBypassLength=4
# Whether add ReLu after each Conv layer (true/false)
includeRelu=0
# Possiblity of doubling channel number in each Conv layer is 1/doubleChannel
doubleChannel=2
# Possiblity of including pooling layer after each Conv layer is 1/includePooling
includePooling=2

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@ -1,41 +0,0 @@
[dse]
# Non-negative number: the number of output pareto designs.
output_num=1
# Positive number: the maximum parallelism of initialization.
max_init_parallel=32
# Positive number: the maximum parallelism of exploration.
max_expl_parallel=128
# Positive number: the maximum parallelism of each loop.
max_loop_parallel=16
# Positive number: the maximum DSE iteration number.
max_iter_num=30
# Positive float number: the maximum distance of the neighbor search.
max_distance=3.0
# Whether only include directive optimizations into the DSE.
directive_only=false
# Whether consider resource constraint during the DSE.
res_constraint=true
[specification]
frequency=100MHz
dsp=220
bram=280
lut=13300
[100MHz]
fadd=4
fmul=3
fdiv=15
fcmp=1
fadd_delay=7.25
fmul_delay=5.7
fdiv_delay=6.07
fcmp_delay=6.4

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@ -38,7 +38,7 @@ def QoREstimation : Pass<"qor-estimation", "ModuleOp"> {
// Design Space Exploration Pass
//===----------------------------------------------------------------------===//
def MultipleLevelDSE : Pass<"multiple-level-dse", "ModuleOp"> {
def MultipleLevelDSE : Pass<"dse", "ModuleOp"> {
let summary = "Optimize HLS design at multiple abstraction level";
let description = [{
This multiple-level-dse pass will automatically conduct the design space