Remove config folder; Update -multiple-level-dse to -dse
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@ -7,7 +7,7 @@ Please check out our [arXiv paper](https://arxiv.org/abs/2107.11673) for more de
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## Quick Start
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### 1. Download and Install ScaleHLS
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To build ScaleHLS, run:
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To build ScaleHLS with HLS C front-end, run:
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```sh
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$ git clone --recursive git@github.com:hanchenye/scalehls.git
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$ mkdir scalehls/build
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@ -37,7 +37,7 @@ $ cd scalehls
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$ # HLS C programs parsing and automatic kernel-level design space exploration.
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$ mlir-clang samples/polybench/gemm/gemm_32.c -function=gemm_32 -memref-fullrank -S | \
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scalehls-opt -multiple-level-dse="top-func=gemm_32 output-path=./ target-spec=config/target-spec.ini" \
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scalehls-opt -dse="top-func=gemm_32 output-path=./ target-spec=samples/polybench/target-spec.ini" \
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-debug-only=scalehls > /dev/null
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$ scalehls-translate -emit-hlscpp gemm_32_pareto_0.mlir > gemm_32_pareto_0.cpp
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@ -1,26 +0,0 @@
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[config]
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# input and output information
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inputChannel=3
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inputHeight=32
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inputWidth=32
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outputChannel=10
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# Generation rules
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batchSize=1
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minChannel=8
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maxChannel=64
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poolingNumber=3
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# Bypass information
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bypassNumber=1
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minBypassLength=2
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maxBypassLength=4
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# Whether add ReLu after each Conv layer (true/false)
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includeRelu=0
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# Possiblity of doubling channel number in each Conv layer is 1/doubleChannel
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doubleChannel=2
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# Possiblity of including pooling layer after each Conv layer is 1/includePooling
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includePooling=2
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@ -1,41 +0,0 @@
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[dse]
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# Non-negative number: the number of output pareto designs.
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output_num=1
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# Positive number: the maximum parallelism of initialization.
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max_init_parallel=32
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# Positive number: the maximum parallelism of exploration.
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max_expl_parallel=128
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# Positive number: the maximum parallelism of each loop.
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max_loop_parallel=16
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# Positive number: the maximum DSE iteration number.
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max_iter_num=30
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# Positive float number: the maximum distance of the neighbor search.
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max_distance=3.0
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# Whether only include directive optimizations into the DSE.
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directive_only=false
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# Whether consider resource constraint during the DSE.
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res_constraint=true
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[specification]
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frequency=100MHz
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dsp=220
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bram=280
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lut=13300
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[100MHz]
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fadd=4
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fmul=3
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fdiv=15
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fcmp=1
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fadd_delay=7.25
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fmul_delay=5.7
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fdiv_delay=6.07
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fcmp_delay=6.4
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@ -38,7 +38,7 @@ def QoREstimation : Pass<"qor-estimation", "ModuleOp"> {
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// Design Space Exploration Pass
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//===----------------------------------------------------------------------===//
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def MultipleLevelDSE : Pass<"multiple-level-dse", "ModuleOp"> {
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def MultipleLevelDSE : Pass<"dse", "ModuleOp"> {
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let summary = "Optimize HLS design at multiple abstraction level";
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let description = [{
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This multiple-level-dse pass will automatically conduct the design space
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