[QoREstimation] unroll loops in IR now! support a real partition-aware loop scheduling
This commit is contained in:
Hanchen Ye
parent
28926c5cc2
commit
cbfb623c67
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@ -9,6 +9,7 @@
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#include "Visitor.h"
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#include "mlir/Dialect/Affine/IR/AffineOps.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/LoopUtils.h"
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#include "llvm/ADT/TypeSwitch.h"
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namespace mlir {
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@ -23,24 +24,46 @@ public:
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explicit HLSCppToolBase(OpBuilder &builder) : builder(builder) {}
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/// Get value methods.
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int64_t getIntAttrValue(Operation *op, StringRef name) {
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if (auto attr = op->getAttrOfType<IntegerAttr>(name))
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return attr.getInt();
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else
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return -1;
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}
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unsigned getUIntAttrValue(Operation *op, StringRef name) {
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return op->getAttrOfType<IntegerAttr>(name).getUInt();
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if (auto attr = op->getAttrOfType<IntegerAttr>(name))
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return attr.getUInt();
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else
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return 0;
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}
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bool getBoolAttrValue(Operation *op, StringRef name) {
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return op->getAttrOfType<BoolAttr>(name).getValue();
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if (auto attr = op->getAttrOfType<BoolAttr>(name))
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return attr.getValue();
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else
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return false;
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}
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StringRef getStrAttrValue(Operation *op, StringRef name) {
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return op->getAttrOfType<StringAttr>(name).getValue();
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if (auto attr = op->getAttrOfType<StringAttr>(name))
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return attr.getValue();
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else
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return "";
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}
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StringRef getPartitionType(ArrayOp *op, unsigned dim) {
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return op->partition_type()[dim].cast<StringAttr>().getValue();
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StringRef getPartitionType(ArrayOp op, unsigned dim) {
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if (auto attr = op.partition_type()[dim].cast<StringAttr>())
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return attr.getValue();
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else
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return "";
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}
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unsigned getPartitionFactor(ArrayOp *op, unsigned dim) {
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return op->partition_factor()[dim].cast<IntegerAttr>().getUInt();
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unsigned getPartitionFactor(ArrayOp op, unsigned dim) {
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if (auto attr = op.partition_factor()[dim].cast<IntegerAttr>())
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return attr.getUInt();
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else
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return 0;
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}
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/// Set value methods.
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@ -48,6 +71,10 @@ public:
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op->setAttr(name, builder.getUI32IntegerAttr(value));
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}
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void setAttrValue(Operation *op, StringRef name, int32_t value) {
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op->setAttr(name, builder.getI32IntegerAttr(value));
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}
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void setAttrValue(Operation *op, StringRef name, bool value) {
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op->setAttr(name, builder.getBoolAttr(value));
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}
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@ -65,11 +92,10 @@ public:
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return getAffineDimExpr(value, builder.getContext());
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}
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AffineExpr getConstExpr(unsigned value) {
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AffineExpr getConstExpr(int64_t value) {
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return getAffineConstantExpr(value, builder.getContext());
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}
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private:
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OpBuilder &builder;
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};
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@ -97,20 +123,30 @@ public:
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// HLSCppEstimator Class Declaration
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//===----------------------------------------------------------------------===//
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// For storing the scheduled time stamp of operations.
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using OpScheduleMap = llvm::SmallDenseMap<Operation *, unsigned, 16>;
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// Indicate the unoccupied memory ports number.
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struct PortNum {
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PortNum(unsigned rdPort = 0, unsigned wrPort = 0, unsigned rdwrPort = 0)
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: rdPort(rdPort), wrPort(wrPort), rdwrPort(rdwrPort) {}
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// For storing each memory access operations indexed by its targed memory
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// value symbol.
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using MemAccess = SmallVector<Operation *, 4>;
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using MemAccessDict = llvm::SmallDenseMap<Value, MemAccess, 16>;
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unsigned rdPort;
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unsigned wrPort;
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unsigned rdwrPort;
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};
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// For storing memory access and schedule information of pipelined region.
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struct PipelineInfo {
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PipelineInfo(unsigned baseII) : II(baseII) {}
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// For storing ports number information of each memory instance.
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using MemPort = llvm::SmallDenseMap<Operation *, SmallVector<PortNum, 16>, 8>;
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unsigned II;
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OpScheduleMap opScheduleMap;
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// For storing MemPort indexed by the pipeline stage (a basic block).
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using MemPortList = SmallVector<MemPort, 16>;
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// For storing each memory access operations (including AffineLoadOp and
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// AffineStoreOp) indexed by the array instantce (ArrayOp).
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using MemAccess = SmallVector<Operation *, 16>;
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using MemAccessDict = llvm::SmallDenseMap<Operation *, MemAccess, 8>;
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// An aggregate information structure for storing memory load and store
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// MemAccessDict in the scope of loop/function/other region.
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struct MemInfo {
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MemAccessDict memLoadDict;
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MemAccessDict memStoreDict;
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};
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@ -126,11 +162,6 @@ struct InductionInfo {
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};
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using InductionInfoList = SmallVector<InductionInfo, 8>;
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// This records the number of accesses for each partition.
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using AccessNum = SmallVector<unsigned, 16>;
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// This records the AccessNum of each dimension of an array.
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using AccessNumList = SmallVector<AccessNum, 8>;
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class HLSCppEstimator : public HLSCppVisitorBase<HLSCppEstimator, bool>,
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public HLSCppToolBase {
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public:
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@ -143,14 +174,12 @@ public:
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bool visitOp(AffineForOp op);
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bool visitOp(AffineIfOp op);
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void setBlockSchedule(Block &block, unsigned opSchedule,
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OpScheduleMap &opScheduleMap);
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unsigned getBlockSchedule(Block &block, bool innerFlatten,
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OpScheduleMap &opScheduleMap);
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int32_t getPartitionIdx(AffineMap map, ArrayOp op);
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void getMemInfo(Block &block, MemInfo &info);
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void getPipelineInfo(Block &block, PipelineInfo &info);
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template <typename OpType> void getAccessNum(OpType op, ArrayOp arrayOp);
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unsigned getLoadStoreSchedule(Operation *op, ArrayOp arrayOp,
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MemPortList &memPortList, unsigned begin);
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unsigned getBlockSchedule(Block &block, MemInfo memInfo);
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void estimateOperation(Operation *op);
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void estimateFunc(FuncOp func);
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@ -5,6 +5,7 @@
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#include "Analysis/QoREstimation.h"
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#include "Analysis/Passes.h"
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#include "Dialect/HLSCpp/HLSCpp.h"
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#include "mlir/IR/PatternMatch.h"
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using namespace std;
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using namespace mlir;
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@ -16,14 +17,41 @@ using namespace hlscpp;
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//===----------------------------------------------------------------------===//
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bool HLSCppAnalyzer::visitOp(AffineForOp op) {
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// If the current loop is annotated as unroll, all inner loops and itself are
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// automatically unrolled.
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if (getBoolAttrValue(op, "unroll")) {
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op.emitRemark("this loop and all inner loops are automatically unrolled.");
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op.walk([&](AffineForOp forOp) {
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if (forOp.getLoopBody().getBlocks().size() != 1)
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op.emitError("has zero or more than one basic blocks.");
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loopUnrollFull(forOp);
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});
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return true;
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}
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// If the current loop is annotated as pipeline, all intter loops are
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// automatically unrolled.
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if (getBoolAttrValue(op, "pipeline")) {
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op.emitRemark("all inner loops are automatically unrolled.");
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op.walk([&](AffineForOp forOp) {
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if (forOp != op) {
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if (forOp.getLoopBody().getBlocks().size() != 1)
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op.emitError("has zero or more than one basic blocks.");
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loopUnrollFull(forOp);
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}
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});
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}
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// We assume loop contains a single basic block.
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auto &body = op.getLoopBody();
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if (body.getBlocks().size() != 1)
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op.emitError("has zero or more than one basic blocks.");
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// Recursively analyze all childs.
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// Recursively analyze all inner loops.
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analyzeBlock(body.front());
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// Set an attribute indicating trip count.
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// Set an attribute indicating the trip count. For now, we assume all loops
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// have static loop bound.
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if (!op.hasConstantLowerBound() || !op.hasConstantUpperBound())
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op.emitError("has variable upper or lower bound.");
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@ -31,25 +59,24 @@ bool HLSCppAnalyzer::visitOp(AffineForOp op) {
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(op.getConstantUpperBound() - op.getConstantLowerBound()) / op.getStep();
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setAttrValue(op, "trip_count", tripCount);
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// Set attributes indicating this loop is perfect or not.
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// Set attributes indicating this loop can be flatten or not.
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unsigned opNum = 0;
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unsigned childNum = 0;
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bool childPerfect = false;
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unsigned forNum = 0;
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bool innerFlatten = false;
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for (auto &bodyOp : body.front()) {
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if (!isa<AffineYieldOp>(bodyOp))
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opNum += 1;
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if (auto child = dyn_cast<AffineForOp>(bodyOp)) {
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childNum += 1;
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childPerfect = getBoolAttrValue(child, "perfect");
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if (isa<AffineForOp>(bodyOp)) {
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forNum += 1;
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innerFlatten = getBoolAttrValue(&bodyOp, "flatten");
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}
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}
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if (opNum == 1 && childNum == 1 && childPerfect)
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setAttrValue(op, "perfect", true);
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else if (childNum == 0)
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setAttrValue(op, "perfect", true);
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if (forNum == 0 || (opNum == 1 && innerFlatten))
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setAttrValue(op, "flatten", true);
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else
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setAttrValue(op, "perfect", false);
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setAttrValue(op, "flatten", false);
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return true;
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}
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@ -105,205 +132,200 @@ HLSCppEstimator::HLSCppEstimator(OpBuilder &builder, string targetSpecPath,
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llvm::outs() << latency << "\n";
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}
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void HLSCppEstimator::setBlockSchedule(Block &block, unsigned opSchedule,
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OpScheduleMap &opScheduleMap) {
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/// Calculate the partition index according to the affine map of a memory access
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/// operation, and store the results as attribute.
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int32_t HLSCppEstimator::getPartitionIdx(AffineMap map, ArrayOp op) {
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int32_t partitionIdx = 0;
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unsigned accumFactor = 1;
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unsigned dim = 0;
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for (auto expr : map.getResults()) {
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auto idxExpr = getConstExpr(0);
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unsigned factor = 1;
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if (op.partition()) {
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auto type = getPartitionType(op, dim);
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factor = getPartitionFactor(op, dim);
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if (type == "cyclic")
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idxExpr = expr % getConstExpr(factor);
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else if (type == "block") {
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auto size = op.getType().cast<ShapedType>().getShape()[dim];
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idxExpr = expr.floorDiv(getConstExpr((size + factor - 1) / factor));
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}
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}
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if (auto constExpr = idxExpr.dyn_cast<AffineConstantExpr>()) {
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if (dim == 0)
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partitionIdx = constExpr.getValue();
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else
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partitionIdx += constExpr.getValue() * accumFactor;
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} else {
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partitionIdx = -1;
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break;
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}
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accumFactor *= factor;
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dim += 1;
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}
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return partitionIdx;
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}
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void HLSCppEstimator::getMemInfo(Block &block, MemInfo &info) {
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for (auto &op : block) {
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if (auto child = dyn_cast<AffineForOp>(op))
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setBlockSchedule(child.getRegion().front(), opSchedule, opScheduleMap);
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opScheduleMap[&op] = opSchedule;
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if (auto loadOp = dyn_cast<AffineLoadOp>(op)) {
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auto arrayOp = cast<ArrayOp>(loadOp.getMemRef().getDefiningOp());
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info.memLoadDict[arrayOp].push_back(loadOp);
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setAttrValue(loadOp, "partition_index",
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getPartitionIdx(loadOp.getAffineMap(), arrayOp));
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// TODO: consider RAW, WAR, WAW dependency for scheduling.
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} else if (auto storeOp = dyn_cast<AffineStoreOp>(op)) {
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auto arrayOp = cast<ArrayOp>(storeOp.getMemRef().getDefiningOp());
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info.memLoadDict[arrayOp].push_back(storeOp);
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setAttrValue(storeOp, "partition_index",
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getPartitionIdx(storeOp.getAffineMap(), arrayOp));
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}
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}
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}
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unsigned HLSCppEstimator::getBlockSchedule(Block &block, bool innerUnroll,
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OpScheduleMap &opScheduleMap) {
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unsigned blockSchedule = 0;
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unsigned HLSCppEstimator::getLoadStoreSchedule(Operation *op, ArrayOp arrayOp,
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MemPortList &memPortList,
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unsigned begin) {
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auto partitionIdx = getIntAttrValue(op, "partition_index");
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// Try to avoid memory port violation until a legal schedule is found.
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// Since an infinite length pipeline can be generated, this while loop can
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// be proofed to have an end.
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while (true) {
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auto partitionPortNum = memPortList[begin][arrayOp];
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bool memEmpty = false;
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// Partition factor.
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unsigned factor = 1;
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// If the memory has not been occupied by the current stage, it should
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// be initialized according to its storage type. Note that each
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// partition should have one PortNum structure.
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if (partitionPortNum.empty()) {
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memEmpty = true;
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if (getBoolAttrValue(arrayOp, "partition")) {
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for (unsigned dim = 0;
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dim < arrayOp.getType().cast<ShapedType>().getRank(); ++dim)
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factor *= getPartitionFactor(arrayOp, dim);
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}
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auto storagetType = getStrAttrValue(arrayOp, "storage_type");
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for (unsigned p = 0; p < factor; ++p) {
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unsigned rdPort = 0;
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unsigned wrPort = 0;
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unsigned rdwrPort = 0;
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if (storagetType == "ram_s2p")
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rdPort = 1, wrPort = 1;
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else if (storagetType == "ram_2p" || storagetType == "ram_t2p")
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rdwrPort = 2;
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else if (storagetType == "ram_1p")
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rdwrPort = 1;
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else {
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rdwrPort = 2;
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arrayOp.emitError("unsupported storage type.");
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}
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PortNum portNum(rdPort, wrPort, rdwrPort);
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partitionPortNum.push_back(portNum);
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}
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}
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// TODO: When partition index can't be determined, this operation will be
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// considered to occupy all ports.
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if (partitionIdx == -1) {
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if (memEmpty) {
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for (unsigned p = 0; p < factor; ++p) {
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partitionPortNum[partitionIdx].rdPort = 0;
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partitionPortNum[partitionIdx].wrPort = 0;
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partitionPortNum[partitionIdx].rdwrPort = 0;
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}
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memPortList[begin][arrayOp] = partitionPortNum;
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break;
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} else {
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if (++begin >= memPortList.size()) {
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MemPort memPort;
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memPortList.push_back(memPort);
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}
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}
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}
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// Find whether the current schedule meets memory port limitation. If
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// not, the schedule will increase by 1.
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if (partitionPortNum[partitionIdx].rdPort > 0) {
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partitionPortNum[partitionIdx].rdPort -= 1;
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memPortList[begin][arrayOp] = partitionPortNum;
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break;
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} else if (partitionPortNum[partitionIdx].rdwrPort > 0) {
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partitionPortNum[partitionIdx].rdwrPort -= 1;
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memPortList[begin][arrayOp] = partitionPortNum;
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break;
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} else {
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if (++begin >= memPortList.size()) {
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MemPort memPort;
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memPortList.push_back(memPort);
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}
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}
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}
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return begin;
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}
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unsigned HLSCppEstimator::getBlockSchedule(Block &block, MemInfo memInfo) {
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unsigned blockEnd = 0;
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MemPortList memPortList;
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for (auto &op : block) {
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unsigned opSchedule = 0;
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// Add the latest scheduled time among all predecessors.
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// Find the latest predecessor dominating the current operation. This should
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// be considered as the earliest stage that the current operation can be
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// scheduled.
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unsigned begin = 0;
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unsigned end = 0;
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for (auto operand : op.getOperands()) {
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if (operand.getKind() != Value::Kind::BlockArgument)
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opSchedule = max(opSchedule, opScheduleMap[operand.getDefiningOp()]);
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begin = max(begin,
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getUIntAttrValue(operand.getDefiningOp(), "schedule_end"));
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}
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// Add latency of the current operation.
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unsigned childSchedule = 0;
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if (auto child = dyn_cast<AffineForOp>(op)) {
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if (innerUnroll) {
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setAttrValue(child, "unroll", true);
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setAttrValue(child, "flatten", false);
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childSchedule = getBlockSchedule(child.getRegion().front(),
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/*innerUnroll=*/true, opScheduleMap);
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} else {
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// Two extra clock cycles will be required to enter and exit child loop.
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opSchedule += getUIntAttrValue(child, "latency") + 2;
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setBlockSchedule(child.getRegion().front(), opSchedule, opScheduleMap);
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}
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} else {
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// For now we make a simple assumption tha all standard operations has an
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// unit latency.
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// TODO: Support estimation from profiling data.
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opSchedule += 1;
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// Insert new pipeline stages.
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while (begin >= memPortList.size()) {
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MemPort memPort;
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memPortList.push_back(memPort);
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}
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opScheduleMap[&op] = opSchedule;
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blockSchedule = max({blockSchedule, childSchedule, opSchedule});
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}
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return blockSchedule;
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}
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void HLSCppEstimator::getPipelineInfo(Block &block, PipelineInfo &info) {
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for (auto &op : block) {
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// Handle load operations and RAW dependencies.
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// Handle load operations, ensure the current schedule meets memory port
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// limitation.
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if (auto loadOp = dyn_cast<AffineLoadOp>(op)) {
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for (auto prevOp : info.memStoreDict[loadOp.getMemRef()]) {
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unsigned RAWLatency =
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info.opScheduleMap[loadOp] - info.opScheduleMap[prevOp];
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info.II = max(info.II, RAWLatency);
|
||||
}
|
||||
info.memLoadDict[loadOp.getMemRef()].push_back(loadOp);
|
||||
auto arrayOp = cast<ArrayOp>(loadOp.getMemRef().getDefiningOp());
|
||||
begin = getLoadStoreSchedule(loadOp, arrayOp, memPortList, begin);
|
||||
end = begin + 1;
|
||||
}
|
||||
|
||||
// Handle Store operations and RAW/WAW dependencies.
|
||||
// Handle store operations.
|
||||
else if (auto storeOp = dyn_cast<AffineStoreOp>(op)) {
|
||||
for (auto prevOp : info.memLoadDict[storeOp.getMemRef()]) {
|
||||
unsigned WARLatency =
|
||||
info.opScheduleMap[storeOp] - info.opScheduleMap[prevOp];
|
||||
info.II = max(info.II, WARLatency);
|
||||
}
|
||||
for (auto prevOp : info.memStoreDict[storeOp.getMemRef()]) {
|
||||
unsigned WAWLatency =
|
||||
info.opScheduleMap[storeOp] - info.opScheduleMap[prevOp];
|
||||
info.II = max(info.II, WAWLatency);
|
||||
}
|
||||
info.memStoreDict[storeOp.getMemRef()].push_back(storeOp);
|
||||
auto arrayOp = cast<ArrayOp>(storeOp.getMemRef().getDefiningOp());
|
||||
begin = getLoadStoreSchedule(storeOp, arrayOp, memPortList, begin);
|
||||
end = begin + 1;
|
||||
}
|
||||
// Handle loop operations.
|
||||
else if (auto forOp = dyn_cast<AffineForOp>(op)) {
|
||||
// Child loop is considered as a large node, and two extra clock cycles
|
||||
// will be required to enter and exit the child loop.
|
||||
end = begin + getUIntAttrValue(forOp, "latency") + 2;
|
||||
}
|
||||
// Default case. All normal expressions and operations will be handled by
|
||||
// this branch.
|
||||
else {
|
||||
// TODO: For now, we assume all operations take one clock cycle to
|
||||
// execute, should support to accept profiling data.
|
||||
end = begin + 1;
|
||||
}
|
||||
|
||||
// Recursively handle child loops.
|
||||
else if (auto child = dyn_cast<AffineForOp>(op))
|
||||
getPipelineInfo(child.getRegion().front(), info);
|
||||
}
|
||||
}
|
||||
|
||||
template <typename OpType>
|
||||
void HLSCppEstimator::getAccessNum(OpType op, ArrayOp arrayOp) {
|
||||
InductionInfoList inductionInfoList;
|
||||
SmallVector<AffineExpr, 8> replacements;
|
||||
SmallVector<unsigned, 8> unrollDims;
|
||||
unsigned unrollTripCount = 1;
|
||||
|
||||
// Collect loop information, including induction & unroll information,
|
||||
// and etc. Note that we assume all operands are dims.
|
||||
unsigned operandIdx = 0;
|
||||
for (auto operand : op.getMapOperands()) {
|
||||
if (auto forOp = getForInductionVarOwner(operand)) {
|
||||
auto lowerBound = forOp.getConstantLowerBound();
|
||||
auto upperBound = forOp.getConstantUpperBound();
|
||||
auto step = forOp.getStep();
|
||||
inductionInfoList.push_back(InductionInfo(lowerBound, upperBound, step));
|
||||
|
||||
auto unroll = getBoolAttrValue(forOp, "unroll");
|
||||
auto tripCount = getUIntAttrValue(forOp, "trip_count");
|
||||
if (unroll) {
|
||||
unrollDims.push_back(operandIdx);
|
||||
unrollTripCount *= tripCount;
|
||||
}
|
||||
|
||||
if (unroll)
|
||||
replacements.push_back(getConstExpr(lowerBound));
|
||||
else
|
||||
replacements.push_back(getDimExpr(operandIdx));
|
||||
} else
|
||||
op.emitError("has index constructed by dynamic values.");
|
||||
operandIdx += 1;
|
||||
}
|
||||
|
||||
// Initialize number of accesses for each partition of each array
|
||||
// dimension as zero.
|
||||
AccessNumList accessNumList;
|
||||
for (auto dim : unrollDims) {
|
||||
AccessNum accessNum;
|
||||
if (arrayOp.partition()) {
|
||||
for (unsigned i = 0; i < getPartitionFactor(&arrayOp, dim); ++i)
|
||||
accessNum.push_back(0);
|
||||
} else
|
||||
accessNum.push_back(0);
|
||||
accessNumList.push_back(accessNum);
|
||||
}
|
||||
|
||||
// Trace all possible index to find potential violations regarding
|
||||
// memory ports number. Violations may cause increasement of iteration
|
||||
// latency or initial interval. This will update the accessNumList.
|
||||
for (unsigned i = 0; i < unrollTripCount; ++i) {
|
||||
|
||||
// Calculate number of accesses for each partition of each array dimension.
|
||||
unsigned idx = 0;
|
||||
for (auto dim : unrollDims) {
|
||||
AffineExpr expr = op.getAffineMap().getResult(dim);
|
||||
auto indexExpr = expr.replaceDimsAndSymbols(replacements, {});
|
||||
|
||||
// Calculate which partition is falled in.
|
||||
if (arrayOp.partition()) {
|
||||
auto type = getPartitionType(&arrayOp, dim);
|
||||
auto factor = getPartitionFactor(&arrayOp, dim);
|
||||
if (type == "cyclic")
|
||||
indexExpr = indexExpr % getConstExpr(factor);
|
||||
else if (type == "block") {
|
||||
auto dimSize = arrayOp.getType().cast<ShapedType>().getShape()[dim];
|
||||
indexExpr =
|
||||
indexExpr.floorDiv(getConstExpr((dimSize + factor - 1) / factor));
|
||||
}
|
||||
} else
|
||||
indexExpr = getConstExpr(0);
|
||||
|
||||
// According to partition information.
|
||||
if (auto constExpr = indexExpr.dyn_cast<AffineConstantExpr>()) {
|
||||
auto partitionId = constExpr.getValue();
|
||||
accessNumList[idx][partitionId] += 1;
|
||||
} else {
|
||||
}
|
||||
idx += 1;
|
||||
}
|
||||
|
||||
// Update replacement.
|
||||
unsigned order = 0;
|
||||
for (auto dim : unrollDims) {
|
||||
auto value = replacements[dim].cast<AffineConstantExpr>().getValue();
|
||||
|
||||
// The little-end value will always increase with a stride of
|
||||
// step.
|
||||
if (order == 0)
|
||||
value += inductionInfoList[dim].step;
|
||||
|
||||
// The value of the current dimension should return to lowerBound
|
||||
// if is greater or equal to upperBound.
|
||||
if (value >= inductionInfoList[dim].upperBound) {
|
||||
value = inductionInfoList[dim].lowerBound;
|
||||
|
||||
// Update the value of the next dimension.
|
||||
if (order < unrollDims.size() - 1) {
|
||||
auto nextDim = unrollDims[order + 1];
|
||||
auto nextValue =
|
||||
replacements[nextDim].cast<AffineConstantExpr>().getValue();
|
||||
nextValue += inductionInfoList[nextDim].step;
|
||||
replacements[nextDim] = getConstExpr(nextValue);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the value of the current dimension.
|
||||
replacements[dim] = getConstExpr(value);
|
||||
order += 1;
|
||||
}
|
||||
}
|
||||
|
||||
// update
|
||||
for (auto accessNum : accessNumList) {
|
||||
llvm::outs() << "new dim\n";
|
||||
for (auto num : accessNum) {
|
||||
llvm::outs() << num << "\n";
|
||||
}
|
||||
setAttrValue(&op, "schedule_begin", begin);
|
||||
setAttrValue(&op, "schedule_end", end);
|
||||
blockEnd = max(blockEnd, end);
|
||||
}
|
||||
return blockEnd;
|
||||
}
|
||||
|
||||
bool HLSCppEstimator::visitOp(AffineForOp op) {
|
||||
|
|
@ -311,95 +333,58 @@ bool HLSCppEstimator::visitOp(AffineForOp op) {
|
|||
if (body.getBlocks().size() != 1)
|
||||
op.emitError("has zero or more than one basic blocks.");
|
||||
|
||||
// If loop is unrolled, all inner loops will be unrolled accordingly.
|
||||
if (getBoolAttrValue(op, "unroll")) {
|
||||
setAttrValue(op, "pipeline", false);
|
||||
setAttrValue(op, "flatten", false);
|
||||
op.emitRemark("all inner loops are automatically unrolled.");
|
||||
|
||||
OpScheduleMap opScheduleMap;
|
||||
auto latency =
|
||||
getBlockSchedule(body.front(), /*innerUnroll=*/true, opScheduleMap);
|
||||
setAttrValue(op, "latency", latency);
|
||||
return true;
|
||||
}
|
||||
|
||||
// If loop is pipelined, the pipelined loop will be estimated as a whole since
|
||||
// all loops inside of a pipeline will be automatically fully unrolled.
|
||||
// If the current loop is annotated as pipeline, extra dependency and II
|
||||
// analysis will be executed.
|
||||
if (getBoolAttrValue(op, "pipeline")) {
|
||||
setAttrValue(op, "flatten", true);
|
||||
op.emitRemark("all inner loops are automatically unrolled.");
|
||||
MemInfo memInfo;
|
||||
getMemInfo(body.front(), memInfo);
|
||||
|
||||
// Calculate latency of each iteration.
|
||||
PipelineInfo pipelineInfo(/*baseII=*/1);
|
||||
auto iterLatency = getBlockSchedule(body.front(), /*innerUnroll=*/true,
|
||||
pipelineInfo.opScheduleMap);
|
||||
auto iterLatency = getBlockSchedule(body.front(), memInfo);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
|
||||
// For now we make a simple assumption that II is equal to 1.
|
||||
auto tripCount = getUIntAttrValue(op, "trip_count");
|
||||
setAttrValue(op, "flatten_trip_count", tripCount);
|
||||
|
||||
// Collect pipeline information including II and memory access information.
|
||||
getPipelineInfo(body.front(), pipelineInfo);
|
||||
|
||||
// Calculate latency and II considering memory ports violations.
|
||||
for (auto &memLoad : pipelineInfo.memLoadDict) {
|
||||
auto arrayOp = dyn_cast<ArrayOp>(memLoad.first.getDefiningOp());
|
||||
if (!arrayOp)
|
||||
op.emitError("is accessing an array that is not defined by ArrayOp.");
|
||||
|
||||
for (auto loadOp : memLoad.second) {
|
||||
getAccessNum<AffineLoadOp>(cast<AffineLoadOp>(loadOp), arrayOp);
|
||||
}
|
||||
}
|
||||
|
||||
setAttrValue(op, "init_interval", pipelineInfo.II);
|
||||
setAttrValue(op, "latency",
|
||||
iterLatency + pipelineInfo.II * (tripCount - 1));
|
||||
setAttrValue(op, "init_interval", (unsigned)1);
|
||||
setAttrValue(op, "latency", iterLatency + 1 * (tripCount - 1));
|
||||
return true;
|
||||
}
|
||||
|
||||
// If the loop is not pipelined or unrolled, the estimation is different and
|
||||
// requires to recursively enter each child loop for estimating the overall
|
||||
// latency of the current loop.
|
||||
// Recursively estimate all inner loops.
|
||||
estimateBlock(body.front());
|
||||
|
||||
// This simply means the current loop can be flattened into the child loop
|
||||
// pipeline. This will increase the flattened loop trip count without
|
||||
// changing the iteration latency. Note that this will be propogated above
|
||||
// until meeting an imperfect loop.
|
||||
if (getBoolAttrValue(op, "perfect")) {
|
||||
if (auto child = dyn_cast<AffineForOp>(op.getLoopBody().front().front())) {
|
||||
if (getBoolAttrValue(child, "flatten")) {
|
||||
setAttrValue(op, "flatten", true);
|
||||
op.emitRemark("this loop is flattened into its child loop.");
|
||||
if (getBoolAttrValue(op, "flatten")) {
|
||||
auto child = cast<AffineForOp>(op.getLoopBody().front().front());
|
||||
op.emitRemark("this loop is flattened into its inner loop.");
|
||||
|
||||
auto II = getUIntAttrValue(child, "init_interval");
|
||||
auto iterLatency = getUIntAttrValue(child, "iter_latency");
|
||||
auto flattenTripCount = getUIntAttrValue(child, "flatten_trip_count") *
|
||||
getUIntAttrValue(op, "trip_count");
|
||||
auto II = getUIntAttrValue(child, "init_interval");
|
||||
auto iterLatency = getUIntAttrValue(child, "iter_latency");
|
||||
auto flattenTripCount = getUIntAttrValue(child, "flatten_trip_count") *
|
||||
getUIntAttrValue(op, "trip_count");
|
||||
|
||||
setAttrValue(op, "init_interval", II);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
setAttrValue(op, "flatten_trip_count", flattenTripCount);
|
||||
setAttrValue(op, "init_interval", II);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
setAttrValue(op, "flatten_trip_count", flattenTripCount);
|
||||
|
||||
setAttrValue(op, "latency", iterLatency + II * (flattenTripCount - 1));
|
||||
return true;
|
||||
}
|
||||
}
|
||||
setAttrValue(op, "latency", iterLatency + II * (flattenTripCount - 1));
|
||||
}
|
||||
// Default case, aka !pipeline && !flatten.
|
||||
else {
|
||||
MemInfo memInfo;
|
||||
getMemInfo(body.front(), memInfo);
|
||||
|
||||
// Default case, aka !unroll && !pipeline && !(perfect && child.flatten).
|
||||
setAttrValue(op, "flatten", false);
|
||||
auto iterLatency = getBlockSchedule(body.front(), memInfo);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
|
||||
OpScheduleMap opScheduleMap;
|
||||
auto iterLatency =
|
||||
getBlockSchedule(body.front(), /*innerUnroll=*/false, opScheduleMap);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
|
||||
unsigned latency = iterLatency * getUIntAttrValue(op, "trip_count");
|
||||
setAttrValue(op, "latency", latency);
|
||||
unsigned latency = iterLatency * getUIntAttrValue(op, "trip_count");
|
||||
setAttrValue(op, "latency", latency);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -419,9 +404,10 @@ void HLSCppEstimator::estimateFunc(FuncOp func) {
|
|||
|
||||
estimateBlock(func.front());
|
||||
|
||||
OpScheduleMap opScheduleMap;
|
||||
auto latency =
|
||||
getBlockSchedule(func.front(), /*innerUnroll=*/false, opScheduleMap);
|
||||
MemInfo memInfo;
|
||||
getMemInfo(func.front(), memInfo);
|
||||
|
||||
auto latency = getBlockSchedule(func.front(), memInfo);
|
||||
setAttrValue(func, "latency", latency);
|
||||
}
|
||||
|
||||
|
|
@ -447,6 +433,16 @@ struct QoREstimation : public scalehls::QoREstimationBase<QoREstimation> {
|
|||
HLSCppAnalyzer analyzer(builder);
|
||||
analyzer.analyzeModule(getOperation());
|
||||
|
||||
// Canonicalize the analyzed IR.
|
||||
OwningRewritePatternList patterns;
|
||||
|
||||
auto *context = &getContext();
|
||||
for (auto *op : context->getRegisteredOperations())
|
||||
op->getCanonicalizationPatterns(patterns, context);
|
||||
|
||||
Operation *op = getOperation();
|
||||
applyPatternsAndFoldGreedily(op->getRegions(), patterns);
|
||||
|
||||
// Estimate performance and resource utilization.
|
||||
HLSCppEstimator estimator(builder, targetSpec, opLatency);
|
||||
estimator.estimateModule(getOperation());
|
||||
|
|
|
|||
|
|
@ -2,14 +2,12 @@
|
|||
|
||||
// CHECK-LABEL: func @test_for
|
||||
func @test_for(%arg0: memref<16x4x4xindex>, %arg1: memref<16x4x4xindex>) attributes {dataflow = false} {
|
||||
%array0 = "hlscpp.array"(%arg0) {interface = false, storage = false, partition = false} : (memref<16x4x4xindex>) -> memref<16x4x4xindex>
|
||||
%array1 = "hlscpp.array"(%arg1) {interface = false, storage = false, partition = false} : (memref<16x4x4xindex>) -> memref<16x4x4xindex>
|
||||
//"hlscpp.array_pragma" (%arg0) {partition=true, partition_type=["cyclic", "cyclic", "cyclic"], partition_factor=[4 : ui32, 2 : ui32, 4 : ui32], storage_type="ram_2p", interface=true, interface_mode="bram"} : (memref<16x4x4xindex>) -> ()
|
||||
//"hlscpp.array_pragma" (%arg1) {partition=true, partition_type=["cyclic", "cyclic", "cyclic"], partition_factor=[4 : ui32, 2 : ui32, 4 : ui32], storage_type="ram_2p", interface=true, interface_mode="bram"} : (memref<16x4x4xindex>) -> ()
|
||||
%array0 = "hlscpp.array"(%arg0) {interface = false, storage = false, partition=true, partition_type=["cyclic", "cyclic", "cyclic"], partition_factor=[1 : ui32, 1 : ui32, 4 : ui32], storage_type="ram_1p"} : (memref<16x4x4xindex>) -> memref<16x4x4xindex>
|
||||
%array1 = "hlscpp.array"(%arg1) {interface = false, storage = false, partition=true, partition_type=["cyclic", "cyclic", "cyclic"], partition_factor=[1 : ui32, 1 : ui32, 4 : ui32], storage_type="ram_1p"} : (memref<16x4x4xindex>) -> memref<16x4x4xindex>
|
||||
affine.for %i = 0 to 16 {
|
||||
affine.for %j = 0 to 4 {
|
||||
affine.for %k = 0 to 4 {
|
||||
%0 = affine.load %array0[%i, %j, %i + %k] : memref<16x4x4xindex>
|
||||
affine.for %k = 0 to 4{
|
||||
%0 = affine.load %array0[%i, %j, %k] : memref<16x4x4xindex>
|
||||
%1 = affine.load %array1[%i, %j, %k] : memref<16x4x4xindex>
|
||||
%2 = muli %0, %1 : index
|
||||
affine.store %2, %array1[%i, %j, %k] : memref<16x4x4xindex>
|
||||
|
|
|
|||
Loading…
Reference in New Issue