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[AffineLoopPerfection] add a constraint for a legal perfection; [HLSCpp] update some attribute definitions; an important flaw is introduing hlscpp.array operation causes storing to argument memrefs has semantic incorrectness. Although this flaw can be handled by hlscpp emitter, and has not caused malignant issues by now, this should be carefully considered and refactored

This commit is contained in:
Hanchen Ye 2021-01-01 13:21:12 -06:00
parent d086c3a2e8
commit 34f32ab2f2
3 changed files with 20 additions and 30 deletions
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40
include/Dialect/HLSCpp/Attributes.td
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@ -28,28 +28,19 @@ def PartitionTypeAttr : StrEnumAttr<"PartitionType", "", [
def PartitionTypeArrayAttr : TypedArrayAttrBase<PartitionTypeAttr, ""> {}
//===----------------------------------------------------------------------===//
// Pragma bind_storage Attributes
// Pragma Interface Attributes (for array ports)
//===----------------------------------------------------------------------===//
// def StorageImplAttr : StrEnumAttr<"StorageImpl", "", [
// StrEnumAttrCase<"bram", 0>,
// StrEnumAttrCase<"lutram", 1>,
// StrEnumAttrCase<"uram", 2>,
// StrEnumAttrCase<"srl", 3>
// ]> {
// let cppNamespace = "::mlir::scalehls::hlscpp";
// }
def InterfaceModeAttr : StrEnumAttr<"InterfaceMode", "", [
StrEnumAttrCase<"bram", 0>,
StrEnumAttrCase<"m_axi", 1>
]> {
let cppNamespace = "::mlir::scalehls::hlscpp";
}
// def StorageTypeAttr : StrEnumAttr<"StorageType", "", [
// StrEnumAttrCase<"fifo", 0>,
// StrEnumAttrCase<"ram_1p", 1>,
// StrEnumAttrCase<"ram_1wnr", 2>,
// StrEnumAttrCase<"ram_2p", 3>,
// StrEnumAttrCase<"ram_s2p", 4>,
// StrEnumAttrCase<"ram_t2p", 5>
// ]> {
// let cppNamespace = "::mlir::scalehls::hlscpp";
// }
//===----------------------------------------------------------------------===//
// Pragma bind_storage Attributes
//===----------------------------------------------------------------------===//
// Currently we only support bram/lut based memory instance.
def StorageTypeAttr : StrEnumAttr<"StorageType", "", [
@ -61,15 +52,4 @@ def StorageTypeAttr : StrEnumAttr<"StorageType", "", [
let cppNamespace = "::mlir::scalehls::hlscpp";
}
//===----------------------------------------------------------------------===//
// Pragma Interface Attributes (for array rather than scalar ports)
//===----------------------------------------------------------------------===//
def InterfaceModeAttr : StrEnumAttr<"InterfaceMode", "", [
StrEnumAttrCase<"bram", 0>,
StrEnumAttrCase<"m_axi", 1>
]> {
let cppNamespace = "::mlir::scalehls::hlscpp";
}
#endif // SCALEHLS_DIALECT_HLSCPP_ATTRIBUTES_TD

2
include/Dialect/HLSCpp/StructureOps.td
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@ -18,6 +18,8 @@ def AssignOp : HLSCppOp<"assign", [SameOperandsAndResultType]> {
let results = (outs AnyType : $output);
}
// Outdated. This is a temporary approach, which will be substituted by a type
// or attribute based approach.
def ArrayOp : HLSCppOp<"array", [SameOperandsAndResultType]> {
let summary = "A C++ array instance";
let description = [{

8
lib/Transforms/AffineLoopPerfection.cpp
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@ -48,6 +48,14 @@ void AffineLoopPerfection::runOnOperation() {
// All operations before the inner loop should be moved to the
// innermost loop, they are collected in frontOps.
if (!frontOps.empty()) {
// TODO: for now, we assume all users are inside of the current loop.
// This is important because if any user is located at inner loops, it
// is required to create a memref for holding the result.
for (auto op : frontOps)
for (auto user : op->getUsers())
if (user->getParentOp() != loop)
return;
// Create AffineIf in the front of the innermost loop.
SmallVector<AffineExpr, 4> ifExprs;
SmallVector<bool, 4> ifEqFlags;