[QoREstimation] impl of getAccessNum method, this will take partition information and count number of accesses for each partition of each dimension of each load/store op, which will help to better estimate II and iteration latency
This commit is contained in:
Hanchen Ye
parent
58655710f5
commit
28926c5cc2
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@ -35,6 +35,14 @@ public:
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return op->getAttrOfType<StringAttr>(name).getValue();
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}
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StringRef getPartitionType(ArrayOp *op, unsigned dim) {
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return op->partition_type()[dim].cast<StringAttr>().getValue();
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}
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unsigned getPartitionFactor(ArrayOp *op, unsigned dim) {
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return op->partition_factor()[dim].cast<IntegerAttr>().getUInt();
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}
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/// Set value methods.
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void setAttrValue(Operation *op, StringRef name, unsigned value) {
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op->setAttr(name, builder.getUI32IntegerAttr(value));
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@ -48,6 +56,19 @@ public:
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op->setAttr(name, builder.getStringAttr(value));
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}
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/// Get expression methods.
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AffineExpr getSymbolExpr(unsigned value) {
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return getAffineSymbolExpr(value, builder.getContext());
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}
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AffineExpr getDimExpr(unsigned value) {
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return getAffineDimExpr(value, builder.getContext());
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}
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AffineExpr getConstExpr(unsigned value) {
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return getAffineConstantExpr(value, builder.getContext());
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}
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private:
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OpBuilder &builder;
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};
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@ -61,8 +82,6 @@ class HLSCppAnalyzer : public HLSCppVisitorBase<HLSCppAnalyzer, bool>,
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public:
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explicit HLSCppAnalyzer(OpBuilder &builder) : HLSCppToolBase(builder) {}
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bool inPipeline;
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bool visitUnhandledOp(Operation *op) { return true; }
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using HLSCppVisitorBase::visitOp;
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@ -78,45 +97,61 @@ public:
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// HLSCppEstimator Class Declaration
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//===----------------------------------------------------------------------===//
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// For storing the scheduled time stamp of operations.
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using OpScheduleMap = llvm::SmallDenseMap<Operation *, unsigned, 16>;
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// For storing each memory access operations indexed by its targed memory
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// value symbol.
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using MemAccess = SmallVector<Operation *, 4>;
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using MemAccessDict = llvm::SmallDenseMap<Value, MemAccess, 16>;
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// For storing memory access and schedule information of pipelined region.
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struct PipelineInfo {
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PipelineInfo(unsigned baseII) : II(baseII) {}
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unsigned II;
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OpScheduleMap opScheduleMap;
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MemAccessDict memLoadDict;
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MemAccessDict memStoreDict;
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};
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// For storing loop induction information.
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struct InductionInfo {
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InductionInfo(unsigned lowerBound, unsigned upperBound, unsigned step)
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: lowerBound(lowerBound), upperBound(upperBound), step(step) {}
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unsigned lowerBound;
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unsigned upperBound;
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unsigned step;
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};
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using InductionInfoList = SmallVector<InductionInfo, 8>;
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// This records the number of accesses for each partition.
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using AccessNum = SmallVector<unsigned, 16>;
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// This records the AccessNum of each dimension of an array.
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using AccessNumList = SmallVector<AccessNum, 8>;
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class HLSCppEstimator : public HLSCppVisitorBase<HLSCppEstimator, bool>,
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public HLSCppToolBase {
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public:
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explicit HLSCppEstimator(OpBuilder &builder, std::string targetSpecPath,
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std::string opLatencyPath);
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// For storing the scheduled time stamp of operations;
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using ScheduleMap = llvm::SmallDenseMap<Operation *, unsigned, 16>;
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// For storing each memory access operations indexed by its targed memory
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// value symbol.
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using MemAccess = std::pair<Value, Operation *>;
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using MemAccessList = SmallVector<MemAccess, 16>;
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// For storing required memory ports for each partition of each array.
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using MemPort = SmallVector<unsigned, 16>;
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using MemPortMap = llvm::SmallDenseMap<Value, MemPort, 16>;
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// This flag indicates that currently the estimator is in a pipelined region,
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// which will impact the estimation strategy.
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bool inPipeline;
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bool visitUnhandledOp(Operation *op) { return true; }
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using HLSCppVisitorBase::visitOp;
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/// These methods can estimate the performance and resource utilization of a
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/// specific MLIR structure, and update them in procParams or memroyParams.
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bool visitOp(AffineForOp op);
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bool visitOp(AffineIfOp op);
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/// These methods are used for searching longest path in a DAG.
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void alignBlockSchedule(Block &block, ScheduleMap &opScheduleMap,
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unsigned opSchedule);
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unsigned getBlockSchedule(Block &block, ScheduleMap &opScheduleMap);
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unsigned getBlockII(Block &block, ScheduleMap &opScheduleMap,
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MemAccessList &memLoadList, MemAccessList &memStoreList,
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unsigned initInterval);
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void setBlockSchedule(Block &block, unsigned opSchedule,
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OpScheduleMap &opScheduleMap);
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unsigned getBlockSchedule(Block &block, bool innerFlatten,
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OpScheduleMap &opScheduleMap);
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void getPipelineInfo(Block &block, PipelineInfo &info);
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template <typename OpType> void getAccessNum(OpType op, ArrayOp arrayOp);
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/// MLIR component estimators.
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void estimateOperation(Operation *op);
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void estimateFunc(FuncOp func);
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void estimateBlock(Block &block);
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@ -22,6 +22,7 @@ def ArrayPragmaOp : HLSCppOp<"array_pragma", [PragmaOpInterface]> {
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DefaultValuedAttr<PositiveUI32Attr, "1024"> : $interface_depth,
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// BindStorage-related attributes.
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DefaultValuedAttr<BoolAttr, "false"> : $storage,
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DefaultValuedAttr<StorageTypeAttr, "ram_2p"> : $storage_type,
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DefaultValuedAttr<StorageImplAttr, "bram"> : $storage_impl,
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@ -50,8 +51,9 @@ def LoopPragmaOp : HLSCppOp<"loop_pragma", [
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DefaultValuedAttr<BoolAttr, "false"> : $pipeline,
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DefaultValuedAttr<PositiveUI32Attr, "1"> : $pipeline_II,
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// Unroll-related attributes.
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DefaultValuedAttr<PositiveUI32Attr, "1"> : $unroll_factor
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// Loop-related attributes.
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DefaultValuedAttr<BoolAttr, "false"> : $flatten,
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DefaultValuedAttr<BoolAttr, "false"> : $unroll
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);
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let assemblyFormat = [{attr-dict}];
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@ -31,18 +31,19 @@ def ArrayOp : HLSCppOp<"array", [SameOperandsAndResultType]> {
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let arguments = (ins Type<IsShapedTypePred> : $input,
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// Interface-related attributes.
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OptionalAttr<BoolAttr> : $interface,
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OptionalAttr<InterfaceModeAttr> : $interface_mode,
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OptionalAttr<PositiveUI32Attr> : $interface_depth,
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DefaultValuedAttr<BoolAttr, "false"> : $interface,
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DefaultValuedAttr<InterfaceModeAttr, "m_axi"> : $interface_mode,
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DefaultValuedAttr<PositiveUI32Attr, "1024"> : $interface_depth,
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// BindStorage-related attributes.
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OptionalAttr<StorageTypeAttr> : $storage_type,
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OptionalAttr<StorageImplAttr> : $storage_impl,
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DefaultValuedAttr<BoolAttr, "false"> : $storage,
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DefaultValuedAttr<StorageTypeAttr, "ram_2p"> : $storage_type,
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DefaultValuedAttr<StorageImplAttr, "bram"> : $storage_impl,
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// ArrayPartition-related attributes.
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OptionalAttr<BoolAttr> : $partition,
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OptionalAttr<PartitionTypeArrayAttr> : $partition_type,
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OptionalAttr<PositiveUI32ArrayAttr> : $partition_factor
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DefaultValuedAttr<BoolAttr, "false"> : $partition,
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DefaultValuedAttr<PartitionTypeArrayAttr, "{}"> : $partition_type,
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DefaultValuedAttr<PositiveUI32ArrayAttr, "{}"> : $partition_factor
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);
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let results = (outs Type<IsShapedTypePred> : $output);
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@ -11,10 +11,6 @@ using namespace mlir;
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using namespace scalehls;
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using namespace hlscpp;
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//===----------------------------------------------------------------------===//
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// Utils
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// HLSCppAnalyzer Class Definition
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//===----------------------------------------------------------------------===//
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@ -27,33 +23,30 @@ bool HLSCppAnalyzer::visitOp(AffineForOp op) {
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// Recursively analyze all childs.
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analyzeBlock(body.front());
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// Set an attribute indicating iteration number .
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// Set an attribute indicating trip count.
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if (!op.hasConstantLowerBound() || !op.hasConstantUpperBound())
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op.emitError("has variable upper or lower bound.");
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unsigned iterNumber =
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(op.getConstantUpperBound() - op.getConstantLowerBound()) /
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getUIntAttrValue(op, "unroll_factor") / op.getStep();
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unsigned tripCount =
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(op.getConstantUpperBound() - op.getConstantLowerBound()) / op.getStep();
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setAttrValue(op, "trip_count", tripCount);
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setAttrValue(op, "iter_number", iterNumber);
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// Set an attribute indicating this loop is perfect or not.
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// Set attributes indicating this loop is perfect or not.
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unsigned opNum = 0;
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unsigned loopNum = 0;
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unsigned childNum = 0;
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bool childPerfect = false;
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for (auto &bodyOp : body.front()) {
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if (!isa<AffineYieldOp>(bodyOp))
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opNum += 1;
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if (auto child = dyn_cast<AffineForOp>(bodyOp)) {
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loopNum += 1;
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childNum += 1;
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childPerfect = getBoolAttrValue(child, "perfect");
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}
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}
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if (opNum == 1 && loopNum == 1 && childPerfect)
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if (opNum == 1 && childNum == 1 && childPerfect)
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setAttrValue(op, "perfect", true);
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else if (loopNum == 0)
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else if (childNum == 0)
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setAttrValue(op, "perfect", true);
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else
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setAttrValue(op, "perfect", false);
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@ -96,8 +89,6 @@ HLSCppEstimator::HLSCppEstimator(OpBuilder &builder, string targetSpecPath,
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string opLatencyPath)
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: HLSCppToolBase(builder) {
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inPipeline = false;
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INIReader targetSpec(targetSpecPath);
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if (targetSpec.ParseError())
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llvm::outs() << "error: target spec file parse fail, please refer to "
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@ -114,18 +105,17 @@ HLSCppEstimator::HLSCppEstimator(OpBuilder &builder, string targetSpecPath,
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llvm::outs() << latency << "\n";
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}
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void HLSCppEstimator::alignBlockSchedule(Block &block,
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ScheduleMap &opScheduleMap,
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unsigned opSchedule) {
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void HLSCppEstimator::setBlockSchedule(Block &block, unsigned opSchedule,
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OpScheduleMap &opScheduleMap) {
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for (auto &op : block) {
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if (auto child = dyn_cast<mlir::AffineForOp>(op))
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alignBlockSchedule(child.getRegion().front(), opScheduleMap, opSchedule);
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if (auto child = dyn_cast<AffineForOp>(op))
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setBlockSchedule(child.getRegion().front(), opSchedule, opScheduleMap);
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opScheduleMap[&op] = opSchedule;
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}
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}
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unsigned HLSCppEstimator::getBlockSchedule(Block &block,
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ScheduleMap &opScheduleMap) {
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unsigned HLSCppEstimator::getBlockSchedule(Block &block, bool innerUnroll,
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OpScheduleMap &opScheduleMap) {
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unsigned blockSchedule = 0;
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for (auto &op : block) {
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@ -139,14 +129,17 @@ unsigned HLSCppEstimator::getBlockSchedule(Block &block,
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// Add latency of the current operation.
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unsigned childSchedule = 0;
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if (auto child = dyn_cast<mlir::AffineForOp>(op)) {
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opSchedule += getUIntAttrValue(child, "latency");
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if (inPipeline)
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childSchedule =
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getBlockSchedule(child.getRegion().front(), opScheduleMap);
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else
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alignBlockSchedule(child.getRegion().front(), opScheduleMap,
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opSchedule);
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if (auto child = dyn_cast<AffineForOp>(op)) {
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if (innerUnroll) {
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setAttrValue(child, "unroll", true);
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setAttrValue(child, "flatten", false);
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childSchedule = getBlockSchedule(child.getRegion().front(),
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/*innerUnroll=*/true, opScheduleMap);
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} else {
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// Two extra clock cycles will be required to enter and exit child loop.
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opSchedule += getUIntAttrValue(child, "latency") + 2;
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setBlockSchedule(child.getRegion().front(), opSchedule, opScheduleMap);
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}
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} else {
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// For now we make a simple assumption tha all standard operations has an
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// unit latency.
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@ -160,52 +153,157 @@ unsigned HLSCppEstimator::getBlockSchedule(Block &block,
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return blockSchedule;
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}
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unsigned HLSCppEstimator::getBlockII(Block &block, ScheduleMap &opScheduleMap,
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MemAccessList &memLoadList,
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MemAccessList &memStoreList,
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unsigned initInterval) {
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void HLSCppEstimator::getPipelineInfo(Block &block, PipelineInfo &info) {
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for (auto &op : block) {
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// Handle load operations.
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// Handle load operations and RAW dependencies.
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if (auto loadOp = dyn_cast<AffineLoadOp>(op)) {
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for (auto memStore : memStoreList) {
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if (loadOp.getMemRef() == memStore.first) {
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// TODO: For now, we simply assume the distance between dependency
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// always takes 1. Thus the II is equal to the latency between
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// dependency.
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unsigned RAWLatency =
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opScheduleMap[loadOp] - opScheduleMap[memStore.second];
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initInterval = max(initInterval, RAWLatency);
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}
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for (auto prevOp : info.memStoreDict[loadOp.getMemRef()]) {
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unsigned RAWLatency =
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info.opScheduleMap[loadOp] - info.opScheduleMap[prevOp];
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info.II = max(info.II, RAWLatency);
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}
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memLoadList.push_back(MemAccess(loadOp.getMemRef(), loadOp));
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info.memLoadDict[loadOp.getMemRef()].push_back(loadOp);
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}
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// Handle Store operations.
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// Handle Store operations and RAW/WAW dependencies.
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else if (auto storeOp = dyn_cast<AffineStoreOp>(op)) {
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for (auto memStore : memStoreList) {
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if (loadOp.getMemRef() == memStore.first) {
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unsigned WAWLatency =
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opScheduleMap[storeOp] - opScheduleMap[memStore.second];
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initInterval = max(initInterval, WAWLatency);
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}
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for (auto prevOp : info.memLoadDict[storeOp.getMemRef()]) {
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unsigned WARLatency =
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info.opScheduleMap[storeOp] - info.opScheduleMap[prevOp];
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info.II = max(info.II, WARLatency);
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}
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for (auto memLoad : memLoadList) {
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if (storeOp.getMemRef() == memLoad.first) {
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unsigned WARLatency =
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opScheduleMap[storeOp] - opScheduleMap[memLoad.second];
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initInterval = max(initInterval, WARLatency);
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}
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for (auto prevOp : info.memStoreDict[storeOp.getMemRef()]) {
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unsigned WAWLatency =
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info.opScheduleMap[storeOp] - info.opScheduleMap[prevOp];
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info.II = max(info.II, WAWLatency);
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}
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memStoreList.push_back(MemAccess(storeOp.getMemRef(), storeOp));
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info.memStoreDict[storeOp.getMemRef()].push_back(storeOp);
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}
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// Recursively handle child loops.
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else if (auto child = dyn_cast<AffineForOp>(op))
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initInterval = getBlockII(child.getRegion().front(), opScheduleMap,
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memLoadList, memStoreList, initInterval);
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getPipelineInfo(child.getRegion().front(), info);
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}
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}
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template <typename OpType>
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void HLSCppEstimator::getAccessNum(OpType op, ArrayOp arrayOp) {
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InductionInfoList inductionInfoList;
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SmallVector<AffineExpr, 8> replacements;
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SmallVector<unsigned, 8> unrollDims;
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unsigned unrollTripCount = 1;
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// Collect loop information, including induction & unroll information,
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// and etc. Note that we assume all operands are dims.
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unsigned operandIdx = 0;
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for (auto operand : op.getMapOperands()) {
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if (auto forOp = getForInductionVarOwner(operand)) {
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auto lowerBound = forOp.getConstantLowerBound();
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auto upperBound = forOp.getConstantUpperBound();
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auto step = forOp.getStep();
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inductionInfoList.push_back(InductionInfo(lowerBound, upperBound, step));
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auto unroll = getBoolAttrValue(forOp, "unroll");
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auto tripCount = getUIntAttrValue(forOp, "trip_count");
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if (unroll) {
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unrollDims.push_back(operandIdx);
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unrollTripCount *= tripCount;
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}
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if (unroll)
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replacements.push_back(getConstExpr(lowerBound));
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else
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replacements.push_back(getDimExpr(operandIdx));
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} else
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op.emitError("has index constructed by dynamic values.");
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operandIdx += 1;
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}
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return initInterval;
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// Initialize number of accesses for each partition of each array
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// dimension as zero.
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AccessNumList accessNumList;
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for (auto dim : unrollDims) {
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AccessNum accessNum;
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if (arrayOp.partition()) {
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for (unsigned i = 0; i < getPartitionFactor(&arrayOp, dim); ++i)
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accessNum.push_back(0);
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} else
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accessNum.push_back(0);
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accessNumList.push_back(accessNum);
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}
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// Trace all possible index to find potential violations regarding
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// memory ports number. Violations may cause increasement of iteration
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// latency or initial interval. This will update the accessNumList.
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for (unsigned i = 0; i < unrollTripCount; ++i) {
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// Calculate number of accesses for each partition of each array dimension.
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unsigned idx = 0;
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for (auto dim : unrollDims) {
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AffineExpr expr = op.getAffineMap().getResult(dim);
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auto indexExpr = expr.replaceDimsAndSymbols(replacements, {});
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// Calculate which partition is falled in.
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if (arrayOp.partition()) {
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auto type = getPartitionType(&arrayOp, dim);
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auto factor = getPartitionFactor(&arrayOp, dim);
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if (type == "cyclic")
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indexExpr = indexExpr % getConstExpr(factor);
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else if (type == "block") {
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auto dimSize = arrayOp.getType().cast<ShapedType>().getShape()[dim];
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indexExpr =
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indexExpr.floorDiv(getConstExpr((dimSize + factor - 1) / factor));
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}
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} else
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indexExpr = getConstExpr(0);
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// According to partition information.
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if (auto constExpr = indexExpr.dyn_cast<AffineConstantExpr>()) {
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auto partitionId = constExpr.getValue();
|
||||
accessNumList[idx][partitionId] += 1;
|
||||
} else {
|
||||
}
|
||||
idx += 1;
|
||||
}
|
||||
|
||||
// Update replacement.
|
||||
unsigned order = 0;
|
||||
for (auto dim : unrollDims) {
|
||||
auto value = replacements[dim].cast<AffineConstantExpr>().getValue();
|
||||
|
||||
// The little-end value will always increase with a stride of
|
||||
// step.
|
||||
if (order == 0)
|
||||
value += inductionInfoList[dim].step;
|
||||
|
||||
// The value of the current dimension should return to lowerBound
|
||||
// if is greater or equal to upperBound.
|
||||
if (value >= inductionInfoList[dim].upperBound) {
|
||||
value = inductionInfoList[dim].lowerBound;
|
||||
|
||||
// Update the value of the next dimension.
|
||||
if (order < unrollDims.size() - 1) {
|
||||
auto nextDim = unrollDims[order + 1];
|
||||
auto nextValue =
|
||||
replacements[nextDim].cast<AffineConstantExpr>().getValue();
|
||||
nextValue += inductionInfoList[nextDim].step;
|
||||
replacements[nextDim] = getConstExpr(nextValue);
|
||||
}
|
||||
}
|
||||
|
||||
// Update the value of the current dimension.
|
||||
replacements[dim] = getConstExpr(value);
|
||||
order += 1;
|
||||
}
|
||||
}
|
||||
|
||||
// update
|
||||
for (auto accessNum : accessNumList) {
|
||||
llvm::outs() << "new dim\n";
|
||||
for (auto num : accessNum) {
|
||||
llvm::outs() << num << "\n";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool HLSCppEstimator::visitOp(AffineForOp op) {
|
||||
|
|
@ -213,87 +311,95 @@ bool HLSCppEstimator::visitOp(AffineForOp op) {
|
|||
if (body.getBlocks().size() != 1)
|
||||
op.emitError("has zero or more than one basic blocks.");
|
||||
|
||||
if (getBoolAttrValue(op, "pipeline")) {
|
||||
inPipeline = true;
|
||||
// If loop is unrolled, all inner loops will be unrolled accordingly.
|
||||
if (getBoolAttrValue(op, "unroll")) {
|
||||
setAttrValue(op, "pipeline", false);
|
||||
setAttrValue(op, "flatten", false);
|
||||
op.emitRemark("all inner loops are automatically unrolled.");
|
||||
|
||||
ScheduleMap opScheduleMap;
|
||||
auto iterLatency = getBlockSchedule(body.front(), opScheduleMap);
|
||||
getUIntAttrValue(op, "iter_latency");
|
||||
|
||||
// For now we make a simple assumption that II is equal to 1.
|
||||
auto iterNumber = getUIntAttrValue(op, "iter_number");
|
||||
setAttrValue(op, "pipeline_iter", iterNumber);
|
||||
|
||||
// Calculate initial interval.
|
||||
MemAccessList memLoadList;
|
||||
MemAccessList memStoreList;
|
||||
unsigned initInterval = 1;
|
||||
initInterval = getBlockII(body.front(), opScheduleMap, memLoadList,
|
||||
memStoreList, initInterval);
|
||||
|
||||
// Calculate initial interval caused by limited memory ports. For now, we
|
||||
// just consider the memory access inside of the pipeline region, aks the
|
||||
// extra memory ports caused by unroll optimization out of the pipeline
|
||||
// region are not calculated.
|
||||
MemPortMap memLoadPortMap;
|
||||
MemPortMap memStorePortMap;
|
||||
for (auto &op : body.front()) {
|
||||
}
|
||||
|
||||
setAttrValue(op, "pipeline_II", initInterval);
|
||||
setAttrValue(op, "latency", iterLatency + initInterval * (iterNumber - 1));
|
||||
OpScheduleMap opScheduleMap;
|
||||
auto latency =
|
||||
getBlockSchedule(body.front(), /*innerUnroll=*/true, opScheduleMap);
|
||||
setAttrValue(op, "latency", latency);
|
||||
return true;
|
||||
}
|
||||
|
||||
// If the loop is not pipelined, the estimation is much different and requires
|
||||
// to recursively enter each child loop for estimating the overall latency of
|
||||
// the current loop.
|
||||
else {
|
||||
// Recursively estimate each operation, mainly AffineFor operation will be
|
||||
// differently handled for now.
|
||||
estimateBlock(body.front());
|
||||
// If loop is pipelined, the pipelined loop will be estimated as a whole since
|
||||
// all loops inside of a pipeline will be automatically fully unrolled.
|
||||
if (getBoolAttrValue(op, "pipeline")) {
|
||||
setAttrValue(op, "flatten", true);
|
||||
op.emitRemark("all inner loops are automatically unrolled.");
|
||||
|
||||
// This simply means the current loop can be merged into the child loop
|
||||
// pipeline. This will increase the total IterNumber without changing the
|
||||
// IterLatency.
|
||||
if (inPipeline && getBoolAttrValue(op, "perfect")) {
|
||||
if (auto child = dyn_cast<AffineForOp>(
|
||||
std::next(op.getLoopBody().front().begin()))) {
|
||||
auto initInterval = getUIntAttrValue(child, "pipeline_II");
|
||||
auto iterLatency = getUIntAttrValue(child, "iter_latency");
|
||||
auto pipeIterNumber = getUIntAttrValue(child, "pipeline_iter") *
|
||||
getUIntAttrValue(op, "iter_number");
|
||||
// Calculate latency of each iteration.
|
||||
PipelineInfo pipelineInfo(/*baseII=*/1);
|
||||
auto iterLatency = getBlockSchedule(body.front(), /*innerUnroll=*/true,
|
||||
pipelineInfo.opScheduleMap);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
|
||||
setAttrValue(op, "pipeline_II", initInterval);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
setAttrValue(op, "pipeline_iter", pipeIterNumber);
|
||||
// For now we make a simple assumption that II is equal to 1.
|
||||
auto tripCount = getUIntAttrValue(op, "trip_count");
|
||||
setAttrValue(op, "flatten_trip_count", tripCount);
|
||||
|
||||
setAttrValue(op, "latency",
|
||||
iterLatency + initInterval * (pipeIterNumber - 1));
|
||||
} else {
|
||||
inPipeline = false;
|
||||
op.emitError("is not a perfect loop.");
|
||||
// Collect pipeline information including II and memory access information.
|
||||
getPipelineInfo(body.front(), pipelineInfo);
|
||||
|
||||
// Calculate latency and II considering memory ports violations.
|
||||
for (auto &memLoad : pipelineInfo.memLoadDict) {
|
||||
auto arrayOp = dyn_cast<ArrayOp>(memLoad.first.getDefiningOp());
|
||||
if (!arrayOp)
|
||||
op.emitError("is accessing an array that is not defined by ArrayOp.");
|
||||
|
||||
for (auto loadOp : memLoad.second) {
|
||||
getAccessNum<AffineLoadOp>(cast<AffineLoadOp>(loadOp), arrayOp);
|
||||
}
|
||||
}
|
||||
|
||||
// This branch take cares of all unpipelined or imperfect loops.
|
||||
else {
|
||||
inPipeline = false;
|
||||
setAttrValue(op, "init_interval", pipelineInfo.II);
|
||||
setAttrValue(op, "latency",
|
||||
iterLatency + pipelineInfo.II * (tripCount - 1));
|
||||
return true;
|
||||
}
|
||||
|
||||
ScheduleMap opScheduleMap;
|
||||
auto iterLatency = getBlockSchedule(body.front(), opScheduleMap);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
// If the loop is not pipelined or unrolled, the estimation is different and
|
||||
// requires to recursively enter each child loop for estimating the overall
|
||||
// latency of the current loop.
|
||||
estimateBlock(body.front());
|
||||
|
||||
// For now we follow the COMBA approach for unrooled loops.
|
||||
unsigned latency = iterLatency;
|
||||
if (getUIntAttrValue(op, "iter_number") != 1)
|
||||
latency *= getUIntAttrValue(op, "iter_number") *
|
||||
getUIntAttrValue(op, "unroll_factor");
|
||||
setAttrValue(op, "latency", latency);
|
||||
// This simply means the current loop can be flattened into the child loop
|
||||
// pipeline. This will increase the flattened loop trip count without
|
||||
// changing the iteration latency. Note that this will be propogated above
|
||||
// until meeting an imperfect loop.
|
||||
if (getBoolAttrValue(op, "perfect")) {
|
||||
if (auto child = dyn_cast<AffineForOp>(op.getLoopBody().front().front())) {
|
||||
if (getBoolAttrValue(child, "flatten")) {
|
||||
setAttrValue(op, "flatten", true);
|
||||
op.emitRemark("this loop is flattened into its child loop.");
|
||||
|
||||
// TODO: Calculate initial interval.
|
||||
setAttrValue(op, "iter_latency", (unsigned)1);
|
||||
auto II = getUIntAttrValue(child, "init_interval");
|
||||
auto iterLatency = getUIntAttrValue(child, "iter_latency");
|
||||
auto flattenTripCount = getUIntAttrValue(child, "flatten_trip_count") *
|
||||
getUIntAttrValue(op, "trip_count");
|
||||
|
||||
setAttrValue(op, "init_interval", II);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
setAttrValue(op, "flatten_trip_count", flattenTripCount);
|
||||
|
||||
setAttrValue(op, "latency", iterLatency + II * (flattenTripCount - 1));
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Default case, aka !unroll && !pipeline && !(perfect && child.flatten).
|
||||
setAttrValue(op, "flatten", false);
|
||||
|
||||
OpScheduleMap opScheduleMap;
|
||||
auto iterLatency =
|
||||
getBlockSchedule(body.front(), /*innerUnroll=*/false, opScheduleMap);
|
||||
setAttrValue(op, "iter_latency", iterLatency);
|
||||
|
||||
unsigned latency = iterLatency * getUIntAttrValue(op, "trip_count");
|
||||
setAttrValue(op, "latency", latency);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -313,8 +419,9 @@ void HLSCppEstimator::estimateFunc(FuncOp func) {
|
|||
|
||||
estimateBlock(func.front());
|
||||
|
||||
ScheduleMap opScheduleMap;
|
||||
auto latency = getBlockSchedule(func.front(), opScheduleMap);
|
||||
OpScheduleMap opScheduleMap;
|
||||
auto latency =
|
||||
getBlockSchedule(func.front(), /*innerUnroll=*/false, opScheduleMap);
|
||||
setAttrValue(func, "latency", latency);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,8 @@ static void convertBlock(Block &block) {
|
|||
bool insertArrayOp = false;
|
||||
if (operand.getKind() == Value::Kind::BlockArgument)
|
||||
insertArrayOp = true;
|
||||
else if (!isa<ArrayOp>(operand.getDefiningOp())) {
|
||||
else if (!isa<ArrayOp>(operand.getDefiningOp()) &&
|
||||
!isa<AssignOp>(operand.getDefiningOp())) {
|
||||
insertArrayOp = true;
|
||||
if (!arrayType.hasStaticShape())
|
||||
operand.getDefiningOp()->emitError(
|
||||
|
|
@ -51,8 +52,7 @@ static void convertBlock(Block &block) {
|
|||
// bram. Other attributes are not set here since they requires more
|
||||
// analysis to be determined.
|
||||
arrayOp.setAttr("interface", builder.getBoolAttr(false));
|
||||
arrayOp.setAttr("storage_type", builder.getStringAttr("ram_1p"));
|
||||
arrayOp.setAttr("storage_impl", builder.getStringAttr("bram"));
|
||||
arrayOp.setAttr("storage", builder.getBoolAttr(false));
|
||||
arrayOp.setAttr("partition", builder.getBoolAttr(false));
|
||||
}
|
||||
}
|
||||
|
|
@ -64,8 +64,8 @@ static void convertBlock(Block &block) {
|
|||
|
||||
// Set loop pragma attributes.
|
||||
forOp.setAttr("pipeline", builder.getBoolAttr(false));
|
||||
forOp.setAttr("pipeline_II", builder.getUI32IntegerAttr(1));
|
||||
forOp.setAttr("unroll_factor", builder.getUI32IntegerAttr(1));
|
||||
forOp.setAttr("unroll", builder.getBoolAttr(false));
|
||||
forOp.setAttr("flatten", builder.getBoolAttr(false));
|
||||
|
||||
convertBlock(forOp.getLoopBody().front());
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1034,20 +1034,18 @@ void ModuleEmitter::emitArray(ArrayOp *op) {}
|
|||
|
||||
/// Pragma operation emitters.
|
||||
void ModuleEmitter::emitLoopPragma(LoopPragmaOp *op) {
|
||||
indent();
|
||||
os << "#pragma HLS unroll";
|
||||
// TODO: default factor.
|
||||
os << " factor=" << op->unroll_factor();
|
||||
os << " skip_exit_check\n";
|
||||
|
||||
indent();
|
||||
os << "#pragma HLS pipeline";
|
||||
if (op->pipeline()) {
|
||||
if (op->pipeline())
|
||||
os << " II=" << op->pipeline_II();
|
||||
os << " rewind\n";
|
||||
} else
|
||||
else
|
||||
os << " off\n";
|
||||
|
||||
if (op->unroll()) {
|
||||
indent();
|
||||
os << "#pragma HLS unroll\n";
|
||||
}
|
||||
|
||||
// An empty line.
|
||||
os << "\n";
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,19 +2,19 @@
|
|||
|
||||
// CHECK-LABEL: func @test_for
|
||||
func @test_for(%arg0: memref<16x4x4xindex>, %arg1: memref<16x4x4xindex>) attributes {dataflow = false} {
|
||||
%array0 = "hlscpp.array"(%arg0) {interface = false, partition = false, storage_impl = "bram", storage_type = "ram_1p"} : (memref<16x4x4xindex>) -> memref<16x4x4xindex>
|
||||
%array1 = "hlscpp.array"(%arg1) {interface = false, partition = false, storage_impl = "bram", storage_type = "ram_1p"} : (memref<16x4x4xindex>) -> memref<16x4x4xindex>
|
||||
%array0 = "hlscpp.array"(%arg0) {interface = false, storage = false, partition = false} : (memref<16x4x4xindex>) -> memref<16x4x4xindex>
|
||||
%array1 = "hlscpp.array"(%arg1) {interface = false, storage = false, partition = false} : (memref<16x4x4xindex>) -> memref<16x4x4xindex>
|
||||
//"hlscpp.array_pragma" (%arg0) {partition=true, partition_type=["cyclic", "cyclic", "cyclic"], partition_factor=[4 : ui32, 2 : ui32, 4 : ui32], storage_type="ram_2p", interface=true, interface_mode="bram"} : (memref<16x4x4xindex>) -> ()
|
||||
//"hlscpp.array_pragma" (%arg1) {partition=true, partition_type=["cyclic", "cyclic", "cyclic"], partition_factor=[4 : ui32, 2 : ui32, 4 : ui32], storage_type="ram_2p", interface=true, interface_mode="bram"} : (memref<16x4x4xindex>) -> ()
|
||||
affine.for %i = 0 to 16 {
|
||||
affine.for %j = 0 to 4 {
|
||||
affine.for %k = 0 to 4 {
|
||||
%0 = affine.load %array0[%i, %j, %k] : memref<16x4x4xindex>
|
||||
%0 = affine.load %array0[%i, %j, %i + %k] : memref<16x4x4xindex>
|
||||
%1 = affine.load %array1[%i, %j, %k] : memref<16x4x4xindex>
|
||||
%2 = muli %0, %1 : index
|
||||
affine.store %2, %array1[%i, %j, %k] : memref<16x4x4xindex>
|
||||
} {pipeline = false, pipeline_II = 1 : ui32, unroll_factor = 1 : ui32}
|
||||
} {pipeline = false, pipeline_II = 1 : ui32, unroll_factor = 1 : ui32}
|
||||
} {pipeline = false, pipeline_II = 1 : ui32, unroll_factor = 1 : ui32}
|
||||
} {pipeline = false, unroll = false, flatten = false}
|
||||
} {pipeline = true, unroll = false, flatten = false}
|
||||
} {pipeline = false, unroll = false, flatten = false}
|
||||
return
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,13 +3,15 @@
|
|||
// CHECK-LABEL: func @test_conversion(
|
||||
// CHECK-SAME: %arg0: f32, %arg1: memref<16xf32>) -> (f32, memref<16xf32>, i32, tensor<2x2xi32>) attributes {dataflow = false} {
|
||||
func @test_conversion(%arg0: f32, %arg1: memref<16xf32>) -> (f32, memref<16xf32>, i32, tensor<2x2xi32>) {
|
||||
// CHECK: %[[VAL_0:.*]] = "hlscpp.array"(%[[ARG_1:.*]]) {interface = false, partition = false, storage_impl = "bram", storage_type = "ram_1p"} : (memref<16xf32>) -> memref<16xf32>
|
||||
// CHECK: %[[VAL_0:.*]] = "hlscpp.array"(%[[ARG_1:.*]]) {interface = false, partition = false, storage = false} : (memref<16xf32>) -> memref<16xf32>
|
||||
%c11_i32 = constant 11 : i32
|
||||
%cst = constant dense<[[11, 0], [0, -42]]> : tensor<2x2xi32>
|
||||
|
||||
// CHECK: %[[VAL_1:.*]] = "hlscpp.array"(%cst) {interface = false, partition = false, storage_impl = "bram", storage_type = "ram_1p"} : (tensor<2x2xi32>) -> tensor<2x2xi32>
|
||||
// CHECK: %[[VAL_2:.*]] = "hlscpp.assign"(%[[ARG_0:.*]]) : (f32) -> f32
|
||||
// CHECK: %[[VAL_2:.*]] = "hlscpp.assign"(%c11_i32) : (i32) -> i32
|
||||
// CHECK: return %[[VAL_2:.*]], %[[VAL_0:.*]], %[[VAL_3:.*]], %[[VAL_1:.*]] : f32, memref<16xf32>, i32, tensor<2x2xi32>
|
||||
// CHECK: %[[VAL_1:.*]] = "hlscpp.array"(%cst) {interface = false, partition = false, storage = false} : (tensor<2x2xi32>) -> tensor<2x2xi32>
|
||||
// CHECK: %[[VAL_2:.*]] = "hlscpp.assign"(%arg0) : (f32) -> f32
|
||||
// CHECK: %[[VAL_3:.*]] = "hlscpp.assign"(%[[VAL_0:.*]]) : (memref<16xf32>) -> memref<16xf32>
|
||||
// CHECK: %[[VAL_4:.*]] = "hlscpp.assign"(%c11_i32) : (i32) -> i32
|
||||
// CHECK: %[[VAL_5:.*]] = "hlscpp.assign"(%[[VAL_1:.*]]) : (tensor<2x2xi32>) -> tensor<2x2xi32>
|
||||
// CHECK: return %[[VAL_2:.*]], %[[VAL_3:.*]], %[[VAL_4:.*]], %[[VAL_5:.*]] : f32, memref<16xf32>, i32, tensor<2x2xi32>
|
||||
return %arg0, %arg1, %c11_i32, %cst : f32, memref<16xf32>, i32, tensor<2x2xi32>
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue