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hanchenye-llvm-project
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llvm
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test
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MC
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Disassembler
History
Jiangning Liu
bb60ccf355
Implement AArch64 NEON instruction set AdvSIMD (table).
...
llvm-svn: 194648
2013-11-14 01:57:32 +00:00
..
AArch64
Implement AArch64 NEON instruction set AdvSIMD (table).
2013-11-14 01:57:32 +00:00
ARM
[ARM] Add support for MVFR2 which is new in ARMv8
2013-11-11 19:56:13 +00:00
Mips
Support for microMIPS trap instruction with immediate operands.
2013-11-13 13:15:03 +00:00
SystemZ
[SystemZ] Add the general form of BCR
2013-11-13 16:57:53 +00:00
X86
Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
2013-10-14 01:42:32 +00:00
XCore
[tests] Cleanup initialization of test suffixes.
2013-08-16 00:37:11 +00:00