191 lines
3.2 KiB
C++
191 lines
3.2 KiB
C++
//===-- ARM_DWARF_Registers.h -----------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef utility_ARM_DWARF_Registers_h_
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#define utility_ARM_DWARF_Registers_h_
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enum
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{
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dwarf_r0 = 0,
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dwarf_r1,
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dwarf_r2,
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dwarf_r3,
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dwarf_r4,
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dwarf_r5,
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dwarf_r6,
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dwarf_r7,
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dwarf_r8,
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dwarf_r9,
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dwarf_r10,
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dwarf_r11,
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dwarf_r12,
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dwarf_sp,
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dwarf_lr,
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dwarf_pc,
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dwarf_cpsr,
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dwarf_s0 = 64,
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dwarf_s1,
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dwarf_s2,
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dwarf_s3,
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dwarf_s4,
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dwarf_s5,
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dwarf_s6,
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dwarf_s7,
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dwarf_s8,
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dwarf_s9,
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dwarf_s10,
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dwarf_s11,
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dwarf_s12,
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dwarf_s13,
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dwarf_s14,
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dwarf_s15,
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dwarf_s16,
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dwarf_s17,
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dwarf_s18,
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dwarf_s19,
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dwarf_s20,
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dwarf_s21,
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dwarf_s22,
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dwarf_s23,
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dwarf_s24,
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dwarf_s25,
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dwarf_s26,
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dwarf_s27,
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dwarf_s28,
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dwarf_s29,
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dwarf_s30,
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dwarf_s31,
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// FPA Registers 0-7
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dwarf_f0 = 96,
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dwarf_f1,
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dwarf_f2,
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dwarf_f3,
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dwarf_f4,
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dwarf_f5,
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dwarf_f6,
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dwarf_f7,
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// Intel wireless MMX general purpose registers 0–7
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dwarf_wCGR0 = 104,
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dwarf_wCGR1,
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dwarf_wCGR2,
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dwarf_wCGR3,
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dwarf_wCGR4,
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dwarf_wCGR5,
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dwarf_wCGR6,
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dwarf_wCGR7,
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// XScale accumulator register 0–7 (they do overlap with wCGR0 - wCGR7)
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dwarf_ACC0 = 104,
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dwarf_ACC1,
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dwarf_ACC2,
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dwarf_ACC3,
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dwarf_ACC4,
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dwarf_ACC5,
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dwarf_ACC6,
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dwarf_ACC7,
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// Intel wireless MMX data registers 0–15
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dwarf_wR0 = 112,
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dwarf_wR1,
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dwarf_wR2,
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dwarf_wR3,
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dwarf_wR4,
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dwarf_wR5,
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dwarf_wR6,
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dwarf_wR7,
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dwarf_wR8,
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dwarf_wR9,
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dwarf_wR10,
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dwarf_wR11,
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dwarf_wR12,
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dwarf_wR13,
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dwarf_wR14,
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dwarf_wR15,
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dwarf_spsr = 128,
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dwarf_spsr_fiq,
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dwarf_spsr_irq,
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dwarf_spsr_abt,
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dwarf_spsr_und,
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dwarf_spsr_svc,
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dwarf_r8_usr = 144,
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dwarf_r9_usr,
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dwarf_r10_usr,
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dwarf_r11_usr,
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dwarf_r12_usr,
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dwarf_r13_usr,
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dwarf_r14_usr,
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dwarf_r8_fiq,
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dwarf_r9_fiq,
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dwarf_r10_fiq,
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dwarf_r11_fiq,
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dwarf_r12_fiq,
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dwarf_r13_fiq,
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dwarf_r14_fiq,
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dwarf_r13_irq,
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dwarf_r14_irq,
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dwarf_r13_abt,
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dwarf_r14_abt,
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dwarf_r13_und,
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dwarf_r14_und,
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dwarf_r13_svc,
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dwarf_r14_svc,
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// Intel wireless MMX control register in co-processor 0–7
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dwarf_wC0 = 192,
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dwarf_wC1,
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dwarf_wC2,
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dwarf_wC3,
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dwarf_wC4,
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dwarf_wC5,
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dwarf_wC6,
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dwarf_wC7,
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// VFP-v3/Neon
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dwarf_d0 = 256,
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dwarf_d1,
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dwarf_d2,
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dwarf_d3,
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dwarf_d4,
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dwarf_d5,
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dwarf_d6,
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dwarf_d7,
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dwarf_d8,
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dwarf_d9,
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dwarf_d10,
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dwarf_d11,
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dwarf_d12,
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dwarf_d13,
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dwarf_d14,
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dwarf_d15,
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dwarf_d16,
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dwarf_d17,
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dwarf_d18,
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dwarf_d19,
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dwarf_d20,
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dwarf_d21,
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dwarf_d22,
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dwarf_d23,
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dwarf_d24,
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dwarf_d25,
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dwarf_d26,
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dwarf_d27,
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dwarf_d28,
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dwarf_d29,
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dwarf_d30,
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dwarf_d31
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};
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#endif // utility_ARM_DWARF_Registers_h_
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