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AsmParser
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R600/SI: Add a stub GCNTargetMachine
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2015-01-06 18:00:21 +00:00 |
InstPrinter
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[cleanup] Re-sort all the #include lines in LLVM using
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2015-01-14 11:23:27 +00:00 |
MCTargetDesc
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Revert "Add r224985 back with two fixes."
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2015-01-14 19:07:23 +00:00 |
TargetInfo
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R600/SI: Add a stub GCNTargetMachine
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2015-01-06 18:00:21 +00:00 |
AMDGPU.h
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
AMDGPU.td
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…
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AMDGPUAlwaysInlinePass.cpp
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…
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AMDGPUAsmPrinter.cpp
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R600/SI: Remove VReg_32 register class
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2015-01-07 20:59:25 +00:00 |
AMDGPUAsmPrinter.h
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…
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AMDGPUCallingConv.td
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…
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AMDGPUFrameLowering.cpp
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…
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AMDGPUFrameLowering.h
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…
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AMDGPUISelDAGToDAG.cpp
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R600/SI: Use RegisterOperands to specify which operands can accept immediates
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2015-01-12 19:33:18 +00:00 |
AMDGPUISelLowering.cpp
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Implement new way of expanding extloads.
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2015-01-14 01:35:17 +00:00 |
AMDGPUISelLowering.h
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R600: Implement getRecipEstimate
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2015-01-13 20:53:23 +00:00 |
AMDGPUInstrInfo.cpp
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
AMDGPUInstrInfo.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
AMDGPUInstrInfo.td
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R600/SI: Add class intrinsic
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2015-01-06 23:00:37 +00:00 |
AMDGPUInstructions.td
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R600/SI: Make more unordered comparisons legal
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2014-12-11 22:15:39 +00:00 |
AMDGPUIntrinsicInfo.cpp
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…
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AMDGPUIntrinsicInfo.h
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…
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AMDGPUIntrinsics.td
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…
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AMDGPUMCInstLower.cpp
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
AMDGPUMCInstLower.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
AMDGPUMachineFunction.cpp
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…
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AMDGPUMachineFunction.h
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…
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AMDGPUPromoteAlloca.cpp
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…
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AMDGPURegisterInfo.cpp
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…
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AMDGPURegisterInfo.h
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…
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AMDGPURegisterInfo.td
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…
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AMDGPUSubtarget.cpp
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[cleanup] Re-sort all the #include lines in LLVM using
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2015-01-14 11:23:27 +00:00 |
AMDGPUSubtarget.h
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[cleanup] Re-sort all the #include lines in LLVM using
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2015-01-14 11:23:27 +00:00 |
AMDGPUTargetMachine.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
AMDGPUTargetMachine.h
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R600/SI: Add a stub GCNTargetMachine
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2015-01-06 18:00:21 +00:00 |
AMDGPUTargetTransformInfo.cpp
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…
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AMDILCFGStructurizer.cpp
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…
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AMDKernelCodeT.h
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…
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CIInstructions.td
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…
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CMakeLists.txt
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
CaymanInstructions.td
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…
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EvergreenInstructions.td
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…
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LLVMBuild.txt
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…
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Makefile
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…
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Processors.td
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R600/SI: Define a schedule model
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2015-01-14 01:13:19 +00:00 |
R600ClauseMergePass.cpp
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…
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R600ControlFlowFinalizer.cpp
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…
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R600Defines.h
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…
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R600EmitClauseMarkers.cpp
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…
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R600ExpandSpecialInstrs.cpp
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…
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R600ISelLowering.cpp
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[SelectionDAG] Allow targets to specify legality of extloads' result
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2015-01-08 00:51:32 +00:00 |
R600ISelLowering.h
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…
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R600InstrFormats.td
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…
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R600InstrInfo.cpp
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…
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R600InstrInfo.h
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…
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R600Instructions.td
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R600/SI: Use unordered not equal instructions
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2014-12-11 22:15:35 +00:00 |
R600Intrinsics.td
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…
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R600MachineFunctionInfo.cpp
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…
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R600MachineFunctionInfo.h
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…
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R600MachineScheduler.cpp
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…
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R600MachineScheduler.h
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…
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R600OptimizeVectorRegisters.cpp
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…
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R600Packetizer.cpp
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…
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R600RegisterInfo.cpp
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…
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R600RegisterInfo.h
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…
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R600RegisterInfo.td
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…
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R600Schedule.td
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…
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R600TextureIntrinsicsReplacer.cpp
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…
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R700Instructions.td
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…
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SIAnnotateControlFlow.cpp
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…
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SIDefines.h
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R600/SI: Use RegisterOperands to specify which operands can accept immediates
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2015-01-12 19:33:18 +00:00 |
SIFixSGPRCopies.cpp
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R600/SI: Remove VReg_32 register class
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2015-01-07 20:59:25 +00:00 |
SIFixSGPRLiveRanges.cpp
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…
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SIFoldOperands.cpp
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R600/SI: Add pattern for bitcasting fp immediates to integers
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2015-01-13 22:59:41 +00:00 |
SIISelLowering.cpp
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R600/SI: Fix bad code with unaligned byte vector loads
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2015-01-14 01:35:22 +00:00 |
SIISelLowering.h
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R600/SI: Fix bad code with unaligned byte vector loads
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2015-01-14 01:35:22 +00:00 |
SIInsertWaits.cpp
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R600/SI: Insert s_waitcnt before s_barrier instructions.
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2015-01-06 19:52:07 +00:00 |
SIInstrFormats.td
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R600/SI: Add common class VOPAnyCommon
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2015-01-15 18:42:44 +00:00 |
SIInstrInfo.cpp
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R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI
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2015-01-15 18:43:01 +00:00 |
SIInstrInfo.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
SIInstrInfo.td
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R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
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2015-01-15 18:42:55 +00:00 |
SIInstructions.td
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R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI
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2015-01-15 18:43:01 +00:00 |
SIIntrinsics.td
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…
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SILoadStoreOptimizer.cpp
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…
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SILowerControlFlow.cpp
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R600/SI: Add pattern for bitcasting fp immediates to integers
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2015-01-13 22:59:41 +00:00 |
SILowerI1Copies.cpp
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R600/SI: Remove VReg_32 register class
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2015-01-07 20:59:25 +00:00 |
SIMachineFunctionInfo.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIMachineFunctionInfo.h
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIPrepareScratchRegs.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIRegisterInfo.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIRegisterInfo.h
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIRegisterInfo.td
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R600/SI: Use RegisterOperands to specify which operands can accept immediates
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2015-01-12 19:33:18 +00:00 |
SISchedule.td
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R600/SI: Define a schedule model
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2015-01-14 01:13:19 +00:00 |
SIShrinkInstructions.cpp
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
SITypeRewriter.cpp
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VIInstrFormats.td
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…
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VIInstructions.td
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R600/SI: Remove VReg_32 register class
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2015-01-07 20:59:25 +00:00 |