hanchenye-llvm-project

History

Puyan Lotfi 3ea6b24f41 [MIR-Canon] Don't do vreg skip for independent instructions if there are none. We don't want to create vregs if there is nothing to use them for. That causes verifier errors. Differential Revision: https://reviews.llvm.org/D62740 llvm-svn: 362247		2019-05-31 17:34:25 +00:00
..
AArch64	[MIR-Canon] Skip the first N vreg names lazily.	2019-05-31 06:02:38 +00:00
AMDGPU	[MIR-Canon] Don't do vreg skip for independent instructions if there are none.	2019-05-31 17:34:25 +00:00
ARM	…
Generic	[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL	2018-10-01 21:59:45 +00:00
Hexagon	…
Mips	…
NVPTX	…
PowerPC	[Power9] Allow gpr callee saved spills in prologue to vectors registers	2018-11-09 16:36:24 +00:00
WebAssembly	[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)	2018-05-08 02:02:50 +00:00
X86	[llvm-readobj] Change -long-option to --long-option in tests. NFC	2019-05-01 05:27:20 +00:00
README	…

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.