hanchenye-llvm-project/llvm/test/CodeGen/SPARC
Dan Gohman a5b9645c4b Split the Add, Sub, and Mul instruction opcodes into separate
integer and floating-point opcodes, introducing
FAdd, FSub, and FMul.

For now, the AsmParser, BitcodeReader, and IRBuilder all preserve
backwards compatability, and the Core LLVM APIs preserve backwards
compatibility for IR producers. Most front-ends won't need to change
immediately.

This implements the first step of the plan outlined here:
http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt

llvm-svn: 72897
2009-06-04 22:49:04 +00:00
..
2006-01-22-BitConvertLegalize.ll Split the Add, Sub, and Mul instruction opcodes into separate 2009-06-04 22:49:04 +00:00
2007-05-09-JumpTables.ll
2007-07-05-LiveIntervalAssert.ll
2008-10-10-InlineAsmMemoryOperand.ll Add sparc test for memory operand used in inline asm 2008-10-10 10:15:33 +00:00
2008-10-10-InlineAsmRegOperand.ll Add testcase for 'r' inline asm operand 2008-10-10 20:28:59 +00:00
basictest.ll
ctpop.ll
dg.exp sabre brings to my attention that the 'tr' suffix is also obsolete 2008-05-20 21:00:03 +00:00
private.ll Add the private linkage. 2009-01-15 20:18:42 +00:00
xnor.ll